Maverick EP7312 User Manual Download

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DS508UM1

2.16

LCD Controller with Support for On-Chip Frame Buffer

The LCD controller provides all the necessary control signals to interface directly to a single panel multi-
plexed LCD. The panel size is programmable and can be any width (line length) from 32 to 1024 pixels in
16-pixel increments. The total video frame buffer size is programmable up to 128 kbytes. This equates to
a theoretical maximum panel size of 1024

256 pixels in 4 bits-per-pixel mode. The video frame buffer

can be located in any portion of memory controlled by the chip selects. Its start address will be fixed at
address 0x000.0000 within each chip select. The start address of the LCD video frame buffer is defined in
the FBADDR[3-0] register. These bits become the most significant nibble of the external address bus. The
default start address is 0xC000.0000 (FBADDR = 0xC). A system built using the on-chip SRAM (OCSR),
will then serve as the LCD video frame buffer and miscellaneous data store. The LCD video frame buffer
start address should be set to 0x6 in this option. Programming of the register FBADDR is only permitted
when the LCD is disabled (this is to avoid possible cycle corruption when changing the register contents
while a LCD DMA cycle is in progress). There is no hardware protection to prevent this. It is necessary
for the software to disable the LCD controller before reprogramming the FBADDR register. Full address
decoding is provided for the OCSR, up to the maximum video frame buffer size programmable into the
LCDCON register. Beyond this, the address is wrapped around. The frame buffer start address must not be
programmed to 0x4 or 0x5 if either CL-PS6700 interface is in use (PCMEN1 or PCMEN2 bits in the
SYSCON2 register are enabled). FBADDR should never be programmed to 0x7 or 0x8, as these are the
locations for the on-chip Boot ROM and internal registers.

The screen is mapped to the video frame buffer as one contiguous block where each horizontal line of pix-
els is mapped to a set of consecutive bytes or words in the video RAM. The video frame buffer can be
accessed word wide as pixel 0 is mapped to the LSB in the buffer such that the pixels are arranged in a
little endian manner.

The pixel bit rate, and hence the LCD refresh rate, can be programmed from 18.432 MHz to 576 kHz when
operating in 18.432–73.728 MHz mode, or 13 MHz to 203 kHz when operating from a 13 MHz clock. The
LCD controller is programmed by writing to the LCD control register (LCDCON). The LCDCON register
should not be reprogrammed while the LCD controller is enabled.

The LCD controller also contains two 32-bit palette registers, which allow any 4-, 2-, or 1-bit pixel value
to be mapped to any of the 15 grayscale values available. The required DMA bandwidth to support a ½
VGA panel displaying 4 bits-per-pixel data at an 80 Hz refresh rate is approximately 6.2 Mbytes/s. Assum-
ing the frame buffer is stored in a 32-bit wide memory, the maximum theoretical bandwidth available is
86 Mbytes/s at 36.864 MHz, or 29.7 Mbytes/s at 13 MHz.

The LCD controller uses a nine stage 32-bit wide FIFO to buffer display data. The LCD controller requests
new data when there are five words remaining in the FIFO. This means that for a ½ VGA display at 4 bits-
per-pixel and 80 Hz refresh rate, the maximum allowable DMA latency is approximately 3.25

sec ((5

words

8 bits/byte) / (640

240

4bpp

80 Hz)) = 3.25

s). The worst-case latency is the total number

of cycles from when the DMA request appears to when the first DMA data word actually becomes avail-
able at the FIFO. DMA has the highest priority, so it will always happen next in the system. The maximum
number of cycles required is 36 from the point at which the DMA request occurs to the point at which the
STM is complete, then another 6 cycles before the data actually arrives at the FIFO from the first DMA
read. This creates a total of 42 cycles. Assuming the frame buffer is located in 32-bit wide, the worst-case