56
Virtex-6 FPGA System Monitor
UG370 (v1.1) June 14, 2010
Application Guidelines
INIT_4A => X"0000", -- Sequence register 2
INIT_4B => X"0000", -- Sequence register 3
INIT_4C => X"0000", -- Sequence register 4
INIT_4D => X"0000", -- Sequence register 5
INIT_4E => X"0000", -- Sequence register 6
INIT_4F => X"0000", -- Sequence register 7
INIT_50 => X"0000", -- Alarm limit register 0
INIT_51 => X"0000", -- Alarm limit register 1
INIT_52 => X"E000", -- Alarm limit register 2
INIT_53 => X"0000", -- Alarm limit register 3
INIT_54 => X"0000", -- Alarm limit register 4
INIT_55 => X"0000", -- Alarm limit register 5
INIT_56 => X"CAAA", -- Alarm limit register 6
INIT_57 => X"0000", -- Alarm limit register 7
SIM_MONITOR_FILE => "vccaux_alarm.txt" --Stimulus file for analog simulation
)
port map (
DCLK => clk,
DWE => '0',
DEN => eos,
DADDR => channel_int,
DO => dobus,
CHANNEL => channel,
EOS => eos,
BUSY => busy,
ALM => alm,
RESET=> '0',
CONVST => '0',
CONVSTCLK => '0',
DI => "0000000000000000",
VAUXN => "0000000000000000",
VAUXP=> "0000000000000000",
VN => '0',
VP => '0'
);
end Behavioral;
www.BDTIC.com/XILINX