53
Control Registers
3
Board Control Register Bit Definitions (Continued)
Bits 08 and 07:
Reset[A and B]
- These bits cause the board to return to its
powerup reset state. This reset is a two-step process to ensure
fault tolerance. To initiate a proper reset, the following steps
must be adhered to:
1. Write a logical one (1) to
RESET_A
and a logical zero (0) to
RESET_B
bit.
2. Wait for
RESET_A
bit to be reset by DSP.
3. Write a logical zero (0) to
RESET_A
bit and a logical one (1) to
RESET_B
bit. The maximum time allowed between setting
RESET_A
bit and setting
RESET_B
bit is approximately 2
seconds. If this time is exceeded, the reset sequence must be
performed again. The
RESET_B
bit stays set indicating a reset
did not occur.
Bit 06:
Autozero -
When this bit is set to a logical one (1) by the user, the
inputs from all channels are internally disconnected from the
field and connected to the channel’s analog ground. This bit is
reset automatically by the DSP after new offset coefficients are
determined.
Bit 05:
Data Ready -
This is a status bit informing the user new data is
available in the RAM. The user must reset this bit to a logical zero
(0) after reading the new data.
NOTE:
Polling the Data Ready Flag can cause an increase in noise. Data is updated to
the RAM every 10 msec. The Data Ready Flag should be read after waiting for 10 msec.
Bit 04:
USER COEF -
The user sets this bit if user-defined gain and offset
coefficients are going to be used. This gives the user control of the
gain and offset applied to the raw ADC data. The user must first
write the gain and offset coefficients to the appropriate location
(
$XX80
starting address of offset coefficients and
$XXC0
starting
address for gain coefficients) for the channel(s) of interest. The
gain and offset coefficients are 32 bits wide and must be entered
in two’s complement format. This requires two 16-bit registers.
The coefficients must be entered: the Most Significant Word
(MSW - first 16 bits) followed by the Least Significant Word
(LSW - last 16 bits). For example, gain coefficients for Channel 0
would be entered MSW at
$XXC0
and the LSW at
$XXC2
(see
Table 3-6 on page 54). The
USER COEF
bit is then set informing the
DSP of pending changes. The DSP will load all the coefficients
into its internal memory and use the values during the correction
process. The user-defined values will not be written to the
E
2
PROM unless the user sets the
WRITE COEF
bit located in this
register. This bit is reset after the DSP reads the last coefficient.
Also, the
COEF Status
bit will be set indicating user-defined
coefficients are being used. The DSP will have control of the
internal bus for approximately 21
µ
sec to read in all the
coefficients.
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