CMT2380F17
Rev0.1 | 256/347
www.cmostek.com
SPSTAT
：
SPI Status Register
SFR Page
= 0~F
SFR Address = 0x84
Bit
7
6
5
4
3
2
1
0
Name
SPIF
WCOL
THRF
SPIBSY
MODF
--
--
SPR2
R/W
R/W
R/W
R
R
R/W
W
W
R/W
Reset Value
0
0
0
0
X
X
X
0
Bit 7: SPIF, SPI transfer completion flag
0: The SPIF is cleared in software by writing “1” to this bit.
1: When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if SPI interrupt is
enabled. If nSS pin is driven low when SPI is in master mode with SSIG=0, SPIF will also be set to signal
the “mode change”.
Bit 6: WCOL, SPI write collision flag.
0: The WCOL flag is cleared in software by writing “1” to this bit.
1: The WCOL bit is set if the SPI data register, SPDAT, is written during a data transfer (see Section
“20.2.5 Write Collision”).
Bit 5: THRF, Transmit Holding Register (THR) Full flag. Read only.
0: Means the THR is “empty”. This bit is cleared by hardware when the THR is empty. That means the
data in THR is loaded (by H/W) into the Output Shift Register to be transmitted, and now the user can
write the next data byte to SPDAT for next transmission.
1: Means the THR is “full”. This bit is set by hardware just when SPDAT is written by software.
Bit 4, SPIBSY, SPI Busy flag. Read only.
0: It indicates SPI engine is idle and all shift registers are empty.
1: It is set to logic 1 when a SPI transfer is in progress (Master or slave Mode).
Bit 3: Mode Fault Flag. This bit is set to logic 1 by hardware when a master mode collision is detected
(nSS is low, MSTEN = 1, and SSIG = 0). If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software writing “1”.
Bit 2~1: Res
erved. Software must write “0” on these bits when SPSTAT is written. Bit 0: SPR2, SPI clock
rate select 2 (associated with SPR1 and SPR0)
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
