CMT2380F17
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If the AA flag is reset to “0”, a not acknowledge (high level to TWI0_SDA) will be returned during the
acknowledge clock pulse on TWI0_SCL when:
1)
A data has been received while TWI0/I2C0 is in the master/receiver mode.
2)
A data byte has been received while TWI0/I2C0 is in the addressed slave/receiver mode.
Bit 7, 1~0: CR2, CR1 and CR0, the Clock Rate select Bits
These three bits determine the serial clock frequency when TWI0/I2C0 is in a master mode. The highest
master mode clock frequency is limited to 1MHz. In slave mode, it is no need to select the clock rate.
TWI0/I2C0will automatically synchronize with any clock frequency from master, which is up to 400KHz. The
various serial clock rates are shown in Table 21
–1.
Table 21-1. TWI0/ I2C0 Serial Clock Rates
CR2
CR1
CR0
TWI0
Clock Selection
TWI0
Clock Rate
@ SYSCLK=12MHz
0
0
0
SYSCLK/8
1.5 MHz
0
0
1
SYSCLK/16
750 KHz
0
1
0
SYSCLK/32
375 KHz
0
1
1
SYSCLK/64
187.5 KHz
1
0
0
SYSCLK/128
93.75 KHz
1
0
1
SYSCLK/256
46.875 KHz
1
1
0
S0TOF/6
可变的
1
1
1
T0OF/6
可变的
Note:
1.
The Maximum TWI0/I2C0 clock Rate should under 1MHz, to set SYSCLK = 8MHz to generate 1MHz.
2.
SYSCLK is the system clock.
3.
S0TOF is UART0 Baud-Rate Generator Overflow.
4.
T0OF is Timer 0 Overflow.
意：
SISTA
：
TWI0/ I2C0 Status Register
SFR Page
= 0~F
SFR Address = 0xD3
Bit
7
6
5
4
3
2
1
0
Name
SIS7
SIS6
SIS5
SIS4
SIS3
SIS2
SIS1
SIS0
R/W
R
R
R
R
R
R
R
R
Reset Value
1
1
1
1
1
0
0
0
SISTA is an 8-bit read-only register. The three least significant bits are always 0. The five most significant
bits contain the status code. There are a number of possible status codes. When SISTA contains F8H, no
serial interrupt is requested. All other SISTA values correspond to defined TWI0/ I2C0 states. When each of
these states is entered, a status interrupt is requested (SI=1). A valid status code is present in SISTA when SI
is set by hardware.
In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is
present at an illegal position, such as inside an address/data byte or just on an acknowledge bit.
AUXR3
：
Auxiliary Register 3
SFR Page
= 0 only
SFR Address = 0xA4
Bit
7
6
5
4
3
2
1
0
Name
T0PS1
T0PS0
BPOC1
BPOC0
S0PS0
TWIPS[1:0]
T0XL
Summary of Contents for CMT2380F17
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