CMT2380F17
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8 Direct Memory Access Controller (DMA)
The direct memory access (DMA) controller transfers data from data source to data destination, without
CPU intervention, across the entire XRAM address range and the entire SFR address range. For example,
the DMA controller can move data from the ADC12 conversion result register to 8051 XRAM. This keeps CPU
resources free for other operations.
Using the DMA controller can increase the throughput of peripheral modules. It can also reduce system
power consumption by allowing the CPU to remain in a low-power mode without having to awaken to move
data to or from a peripheral.
The DMA controller features include: Easy use one channel DMA
：
Easy use one channel DMA
Transfer type: Memory to peripheral (M2P), peripheral to memory (P2M), peripheral to peripheral (P2P)
Configurable transfer trigger selections: CPU software or external hardware
Support block transfer mode, transfer sizes up to 65536 transactions
Capability to copy data to CRC engine during DMA transfer
Auto-initialization for circular buffer management (loop mode)
Capability to suspend and resume a DMA transfer.
Capability to operate in low power modes (idle mode for interrupt)
Option interrupt on End of DMA transfer
The DMA access diagram is shown in Figure 8
–1.
SFR Bus
XRAM Bus
Memory to Peripheral(M2P)
CPU SFR Address
CPU XRAM Address
8051 CPU
Peripheral to Peripheral(P2P)
CPU Halt
Bus Arbiter
DMA SFR Address
DMA XRAM Address
DMA
Controller
CRC16
TWI0/I2C0
SPI0
UART1
UART0
XRAM
Area
ADC12
CPU SFR Data
CPU SFR WR
CPU SFR RD
CPU XRAM Data
CPU XRAM WR
CPU XRAM RD
DMA SFR Data
DMA SFR WR
DMA SFR RD
Peripheral to Memory(M2P)
DMA XRAM Data
DMA XRAM WR
DMA XRAM RD
Figure 8-1. DMA DMA Access Diagram
8.1
DMA Structure
In CMT2380F17, the DMA controller provides one channel DMA to support 3 transfer types: transfer the
data from XRAM to peripheral, from peripheral to XRAM and from peripheral to peripheral. DMADS0 register
in DMA channel 0 defines the DMA transfer type to configure DMA controller behavior and defines the data
path to generate the SFR address on peripheral access.
Timer 5 and Timer 6 are embedded in DMA module. The DMA controller supports the block mode
Summary of Contents for CMT2380F17
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