CMT2380F17
Rev0.1 | 75/347
www.cmostek.com
10.3
WDT Register
WDTCR
:
Watch-Dog-Timer Control Register
SFR Page
= 0~F & P
SFR Address = 0xE1
POR = XXX0-XXXX (0000-0111)
Bit
7
6
5
4
3
2
1
0
Name
WREN
NSW
ENW
CLRW
WIDL
PS[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
1
1
1
Bit 7: WREN, WDT Reset Enable. The initial value can be changed by hardware option, WRENO.
0: The overflow of WDT does not set the WDT reset. The WDT overflow flag, WDTF, may be polled
by software or trigger an interrupt.
1: The overflow of WDT will cause a system reset. Once WREN has been set, it can not be cleared
by software in page 0~F.
In page P, software can modify it to
“0” or “1”.
Bit 6: NSW. Non-Stopped WDT. The initial value can be changed by
hardware option, NSWDT. 0: WDT stop counting while the MCU is in
power-down mode.
1: WDT always keeps counting while the MCU is in power-down mode (Watch Mode) or idle
mode. Once NSW has been set, it can not be cleared by software in page 0~F.
In page P,
software can modify it to
“0” or “1”.
Bit 5: ENW. Enable WDT.
0: Disable WDT running. This bit is only cleared by POR.
1: Enable WDT while it is set. Once ENW has been set, it can not be cleared by software in
page 0~F.
In Page P, software can modify it as
“0” or “1”.
Bit 4: CLRW. WDT clear bit.
0: Writing
“0” to this bit is no operation in WDT.
1: Writing “1” to this bit will clear the 8-bit WDT counter to 00H. Note this bit has no need to
be cleared by writing
“0”.Clear WDT to recount while it is set.
Bit 3: WIDL. WDT idle control.
0: WDT stops counting while the
MCU is in idle mode. 1: WDT
keeps counting while the MCU is
in idle mode.
Bit 2~0: PS2 ~ PS0, select prescaler output for WDT time base input.
When WDTFS (CKCON3.4) = 0, WDT clock source= ILRCO or SYSCLK/12
PS[2:0]
Prescaler Value
WDT Period
(WDT clock = ILRCO)
WDT Period
(WDT clock = SYSCLK/12)
(SYSCLK = IHRCO, 12MHz)
0 0 0
2
16 ms
0.512 us
0 0 1
4
32 ms
1.024 ms
0 1 0
8
64 ms
2.048 ms
0 1 1
16
128 ms
4.096 ms
1 0 0
32
256 ms
8.192 ms
1 0 1
64
512 ms
16.384 ms
1 1 0
128
1024 ms
32.768 ms
1 1 1
256
2048 ms
65.536 ms
When WDTFS (CKCON3.4) = 1, WDT clock source= ILRCO
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
