CMT2380F17
Rev0.1 | 72/347
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Bit 5: FWKP, MCU Fast wake up control
0: Select MCU for normal wakeup time about 120us from power-down mode. 1: Select MCU for fast
wakeup time about 30us from power-down mode.
Bit 4: WDTFS. WDT overflow source selection.
0: Select WDT bit-8 overflow as WDT event source. 1: Select WDT bit-0 overflow as WDT event source.
Bit 3~2: MCKD[1:0], MCK Divider Output selection.
MCKD[1:0]
MCKDO
Frequency
Example
MCK = 12MHz
Example
MCK = 48MHz
00
MCKDO = MCK
MCKDO = 12MHz
MCKDO = 48MHz
01
MCKDO = MCK/2
MCKDO = 6MHz
MCKDO = 24MHz
10
MCKDO = MCK/4
MCKDO = 3MHz
MCKDO = 12MHz
11
MCKDO = MCK/8
MCKDO = 1.5MHz
MCKDO = 6MHz
CKCON5: Clock Control Register 5
SFR Page
= P only
SFR Address = 0x43
Bit
7
6
5
4
3
2
1
0
Name
--
--
--
--
--
--
--
CKMS0
R/W
W
W
W
W
W
W
W
R/W
Reset Value
0
0
0
0
0
0
0
0
Bit 7~1: Reserved. Software must write “0” on these bits when CKCON5 is written.
Bit 0: CKMS0, CKM mode selection 0.
0: Select CKM operating for 8X mode. (96MHz)
1: Select CKM operating for 12X mode. (144MHz)
AUXR0: Auxiliary Register 0
SFR Page
= 0~F
SFR Address = 0xA1
Bit
7
6
5
4
3
2
1
0
Name
P60OC[1:0]
P60FD
PBKF
--
INT1H
INT0H
R/W
R/W
R/W
R/W
R/W
W
W
R/W
R/W
Reset Value
0
0
0
X
X
X
0
0
Bit 7~6: P6.0 function configured control bit 1 and 0. The two bits only act when internal RC oscillator
(IHRCO or ILRCO) is selected for system clock source. In external clock input mode, P6.0 is the
dedicated clock input pin. In internal oscillator condition, P6.0 provides the following selections for GPIO
or clock source generator. When P60OC[1:0] index to non-P6.0 GPIO function, P6.0 will drive the on-chip
RC oscillator output to provide the clock source for other devices.
P60OC[1:0]
P60
Function
I/O
Mode
00
P60
By P6M0.0
01
MCK
By P6M0.0
10
MCK/2
By P6M0.0
11
MCK/4
By P6M0.0
For clock-
out on P6.0 function, it is recommended to set P6M0.0 to “1” which selects P6.0 as
push-push output mode.
Bit 5: P60FD, P6.0 Fast Driving.
0: P6.0 output with default driving.
1: P6.0 output with fast driving enabled. If P6.0 is configured to clock output, enable this bit when
P6.0 output frequency is more than 12MHz at 5V application or more than 6MHz at 3V application.
DCON0
:
Device Control Register 0
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
