ERR003749
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
143
Description:
Each Interrupt Status Register contains 32-bit status bits, allowing for the status of 32 individual
interrupt vectors to be reported. The status bits are RW1C bits and are set when an MSI Interrupt
vector is received, and are cleared by software writing a 1 to the bit.
The setting of a status bit takes precedence over the clearing of a status bit. The precedence given
to setting of the status bits resulted in the setting of a single status bit in the register, preventing any
other status bits from being cleared at the same time. As a result, if an MSI interrupt is being logged
in a status bit, and during the same clock cycle, software also attempts to clear another status bit in
the same Status Register, then the status bit corresponding to the MSI interrupt is set but the status
bit being written by software is not cleared and remains set. As a result, even though software has
written a 1 to the status bit, the status bits remains set, reporting that an MSI interrupt has been
received, even though software has serviced the Interrupt Request.
This issue only occurs if the setting of a status bit and the clearing of another status bit within the
same Interrupt Status Register happens during the same clock cycle.
Projected Impact:
A Status bit that has been cleared by Software remains set.
Workarounds:
Read and clear status bit until it is read as cleared.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround not implemented in Linux BSP. Functionality or mode of operation in which
the erratum may manifest itself is not used.
ERR003749
PCIe: 9000426180—MSI Interrupt Controller Status Register bit not
cleared after being written by software
