ERR007265
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
90
NXP Semiconductors
Description:
When software tries to enter Low-Power mode with the following sequence, the SoC enters
Low-Power mode before the ARM core executes the WFI instruction:
1. Set CCM_CLPCR[1:0] to 2’b00
2. ARM core enters WFI
3. ARM core wakeup from an interrupt event, which is masked by GPC or not visible to GPC,
such as an interrupt from a local timer
4. Set CCM_CLPCR[1:0] to 2’b01 or 2’b10
5. ARM core executes WFI
Before the last step, the SoC enters WAIT mode if CCM_CLPCR[1:0] is set to 2’b01, or STOP
mode if CCM_CLPCR[1:0] is set to 2’b10.
Projected Impact:
This issue can lead to errors ranging from module underrun errors to system hangs, depending on
the specific use case.
Workarounds:
Software workaround:
1) Software should trigger IRQ #32 (IOMUX) to be always pending by setting
IOMUX_GPR1_GINT
2) Software should then unmask IRQ #32 in GPC before setting CCM Low-Power mode
3) Software should mask IRQ #32 right after CCM Low-Power mode is set (set bits 0–1 of
CCM_CLPCR)
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround implemented in Linux BSP codebase. A patch is included in both BSP
kernels v3.10.9 and v3.0.35.
ERR007265
CCM: When improper low-power sequence is used, the SoC enters
low power mode before the ARM core executes WFI
