ERR003740
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
47
Description:
The double linefill feature is controlled by bit 30 of the Prefetch Control Register. The L2C-310
cache line length is 32-byte. Therefore, by default, on each L2 cache miss, L2C-310 issues 32-byte
linefills, 4 x 64-bit read bursts, to the L3 memory system. L2C-310 can issue 64-byte linefills
(double linefills), 8 x 64-bit read bursts, on an L2 cache miss. When the L2C-310 is waiting for the
data from L3, it performs a lookup on the second cache line targeted by the 64-byte linefill. When
it misses in the L2 cache, it identifies a victim for future allocation. If such a victim already
contains a dirty entry, the latter must be evicted before the second part of the double linefill is
allocated. For this purpose, the double linefill slot issues a request to the Eviction Buffer. Due to
this erratum, such an eviction request can be missed, leading to the loss of dirty data in the L2
cache.
Conditions:
This problem occurs when the following conditions are met:
• The double linefill feature is enabled.
• The L2 cache contains dirty data.
Projected Impact:
When the conditions above are met and under very rare circumstances depending on the
microarchitecture of L2C-310, the request/ack scheme existing between the Eviction Buffer and
second parts of double linefill slots can go out of sync. As a result, the second part of a double
linefill slot can get allocated into the L2 cache without waiting for the eviction of its victim. Dirty
data are then lost, leading to data corruption.
Workarounds:
The only workaround to this erratum is to disable the double linefill feature. This is the behavior
by default.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround which disables the double linefill feature is integrated in Linux BSP
codebase starting in release imx_3.0.35_4.1.0.
ERR003740
ARM/PL310: 752271—Double linefill feature can cause data
corruption [i.MX 6Dual/6Quad only]
