ERR007926
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
182
NXP Semiconductors
Description:
The internal boot ROM uses the general-purpose timer (GPT) as a timing reference for event and
timeout measurement during the boot process. The ROM uses the 32 kHz clock as the clock source
for the GPT. There will be a short period during device power-up when the SoC will be using the
internal ring oscillator until the crystal oscillator is running. Once the crystal oscillator is running,
the SoC will automatically switch from the internal oscillator to the crystal oscillator.
Consequently, there will be a period of time when the SoC will be booting and using the internal
ring oscillator as its reference clock and the ROM code will be dependent on that clock.
The internal ring oscillator is less accurate than a crystal oscillator and may be up to two times
faster than a 32 kHz external crystal oscillator. The ROM code assumes the reference clock is 32
kHz, so in the presence of a faster reference clock some delays or timeout configurations in the
ROM code will be shorter than expected and may affect SD/MMC boot
, NAND boot,
and One
NAND boot.
NOR and SPI-NOR boot modes are not affected by this issue because these modes do not use
timeouts.
The potential effects are:
1. The SD/MMC card specification may be violated if the SD/MMC card Nac parameter is larger
than 50 ms, or if its initialization time is greater than 500 ms.
2. According to the SD 3.0 specification, the controller should wait a minimum of 5 ms after
disabling SDCLK before re-enabling SDCLK when voltage switching. In the worst case, the
ROM code may only wait 2.5 ms.
3. According to the SD 3.0 specification, the timeout for a CMD6 data transaction response is 100
ms. In the worst case, the ROM code may timeout after 50 ms and therefore not conform to the
specification.
4. One NAND boot may fail if the One NAND memory tRD1 is greater than 1.5 ms.
5. NAND boot may fail if the NAND memory tRST parameter is greater than 11 ms or if its tR
parameter is greater than 1 ms.
Projected Impact:
To date, this failure has not been observed on any system. The description and workarounds
presented here are based on analysis of the timings in the ROM boot sequence and indicates the
possibility that SD/MMC boot
, NAND boot,
or OneNAND boot may be affected. SD/MMC card
specifications may not be met during boot.
Workarounds:
SDMMC boot:
1. SD/MMC: Choose an SD/MMC card for which the Nac parameter is to be specified less than
50 ms and its initialization time is less than 500 ms.
ERR007926
ROM: 32 kHz internal oscillator timing inaccuracy may affect
SD/MMC
,
NAND
,
and OneNAND boot [i.MX 6Dual/6Quad Only]
