ERR004325
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
52
NXP Semiconductors
within the timing window, required to trigger this erratum, might not represent a real case. So, the
erratum trigger in the case of self modifying code is probably restricted to read operations, being
the consequence of either a speculative load, or a “blind” PLD instruction.
In addition, production of data to an agent external from the coherency domain might fail;
particularly, the data target of the cache maintenance operation might not have been made visible
to an external DMA engine when it completes. Again, false sharing on a memory region also
accessed by an external agent, like a DMA engine, is extremely unlikely to exist. As such, the
erratum trigger, when producing data for an external DMA agent, is probably restricted to read
operations, being the consequence of either a speculative load, or a “blind” PLD instruction.
Workarounds:
To work around this erratum, ARM recommends to:
• Ensure there is no false sharing (on a cache line size alignment) for both self modifying code
and data to be cleaned to an external agent, like a DMA engine.
• Set bit[0] in the undocumented SCU diagnostic control register located at offset 0x30 from the
PERIPHBASE address. Setting this bit disables the “migratory bit” feature. This forces a dirty
cache line to be evicted to the lower memory subsystem—which is both the point of coherency
and the point of unification—when it is being read by another processor. Note that this bit can
be written, but is always Read as Zero.
• Insert a DSB instruction in front of the cache maintenance operation. Note that if the cache
maintenance operation is executed within a loop with no other memory operations, ARM only
recommends adding a DSB prior to entering the loop.
Note that the atomicity between the DSB and the cache maintenance operation might not be
ensured because an interrupt may still be taken between the two instructions. However, setting the
“disable migratory line” bit and inserting the DSB in front of the cache maintenance operation will
very significantly decrease the probability to trigger the erratum when false sharing for writes to
either self-modifying code memory regions or DMA regions, on a cache line granularity, which is
likely to be the case.
With these workarounds, the likely occurrence of this erratum is sufficiently low that the erratum
does not limit or severely impair the intended use of specified features.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround integrated in Linux BSP codebase starting in release imx_3.0.35_4.1.0.
