ERR005183
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
56
NXP Semiconductors
Description:
According to the ARM architecture, any change in the Authentication Status Register should be
made visible to the processor after an exception entry or return, or an ISB.
Although this is correctly achieved for all debug-related features, the ISB is not sufficient to make
the changes visible to the trace flow. As a consequence, the WPTTRACEPROHIBITEDn signal(s)
remain stuck to their old value up to the next exception entry or return, or to the next serial branch,
even when an ISB is executed.
A serial branch is one of the following:
• Data processing to PC with the S bit set (for example, MOVS pc, r14)
• LDM pc ^
Projected Impact:
Due to the erratum, the trace flow might not start or stop, as expected by the program.
Workarounds:
To work around the erratum, the ISB must be replaced by one of the events causing the change to
be visible. In particular, replacing the ISB by a MOVS PC to the next instruction will achieve the
correct functionality.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround is not implemented because this erratum will never be encountered in normal
device operation. Users should use ARM recommended workaround if using this debug trace
feature.
ERR005183
ARM/MP: 771224—Visibility of Debug Enable access rights to
enable/disable tracing is not ensured by an ISB
