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Table of Contents
ADC Channel Enable Register .......................................... 20
ADC Clock Divisor Register ............................................... 21
Trigger Mode Register ....................................................... 22
Trigger Level Register........................................................ 23
Trigger Source Register..................................................... 24
Post Trigger Counter Register ........................................... 25
FIFO Status Register ......................................................... 26
FIFO Control Register........................................................ 27
4.10 Acquisition Enable Register ............................................... 28
4.11 Clock Source Register ....................................................... 28
4.12 High Level Programming ................................................... 29
4.13 Low Level Programming .................................................... 29
5 Operation Theory .............................................................. 31
A/D Conversion Procedure ................................................ 31
A/D Signal Source Control ................................................. 32
A/D Trigger Source Control................................................ 32
Trigger Sources ............................................................ 33
Simultaneous Trigger for Multiple Cards ...................... 34
Trigger Modes ............................................................... 35
A/D Clock Source Control .................................................. 37
A/D Clock Sources ........................................................ 37
Internal Pacer Clock ..................................................... 37
External Pacer Clock .................................................... 38
Multiple Cards Operation .............................................. 38
A/D Data Transfer .............................................................. 39
AD Data Transfer .......................................................... 39
Simultaneous Sampling of four AD Channels ............... 39
Total Data Throughput .................................................. 40
Maximum Acquiring Data Length .................................. 40
Bus-mastering Data Transfer ........................................ 41
Host Memory Operation ................................................ 41
Summary ...................................................................... 42
AD Data Format ................................................................. 43
6 C/C++ Library .................................................................... 45
Libraries Installation ........................................................... 45
Programming Guide........................................................... 45
Naming Convention ...................................................... 45
Data Types ................................................................... 46
Summary of Contents for NuDAQ PCI-9810
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