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3--17
Installation and Specifications
The figure below demonstrates how the Internal Control Relays C20--C37 are
mapped to the OP-panel control register. Notice the sixteen bits in the Internal
Control Relays C20--C37 are loaded into the control register. These control relays
function as outputs for the Lights.
LF2
LF3
BD
L1
L2
L3
LF1
Mapping the Control Register
V40601 =
V2015
C20 -- C37
M+13
M+13
Status register
SP1
V40601
V2015
LD
OUT
ON
OP-panel
Register
Internal
Control
Relays
SP1 (always ON) maps OP register
V40601 (C20 --C37) to V2015.
OP--640
M+13
12
13
14
15
8
9
10
11
4
5
6
7
0
1
2
3
C34
C35
C36
C37
C30
C31
C32
C33
C24
C25
C26
C27
C20
C21
C23C22
PLC Program User Memory
LF2
LF3
BD
L1
L2
L3
LF1
Mapping Example (D3--330/340)
Unlike the DL05, DL105, DL205, D3--350, and DL405 mapping examples, the
D3--330/340 CPUs use 8-bit words. So it takes two 8-bit words for each mapped
memory location because each mapped memory location needs sixteen
consecutive bits. We will assume that R400 was used as the base register address
and we want the mapping to start at R16 for the status register.
The figure below demonstrates how the OP-panel status register is mapped to user
memory for bit manipulation. Notice the sixteen bits in the status register are loaded
into the Internal Control Relays C160--C177. These control relays monitor
pushbuttons and coordinate data entry control.
Mapping the Status Register
R430/R431
R16/R17
M+12
M+12
Status register
C374
R430
R16
DSTR
DOUT
ON
OP-panel
Register
Internal
Control
Relays
Not
C374 (always ON after first scan)
maps OP register R430/R431 to R16/R17.
OP--640
M+12
12
13
14
15
8
9
10
11
4
5
6
7
0
1
2
3
C176
C170
C160
PLC Program User Memory
F5
F1
F2
F3
F4
F5
F1
F2
F3
F4
C175
C172
C161
C162
C164
C166
C163
C165
C167
C171
C173
C174
C177
Note that
DSTR and
DOUT are
16-bit
instructions.
Mapping the Control
Register
Mapping the Status
Register