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VERVIEW
826448 V
ERSION
5 M
ARCH
2015
P
ROPRIETARY
1-25
Figure 1.12: CHAMP-AV8 Interrupt Controller Block Diagram
All interrupt source lines are aggregated into the 17 different interrupt source groups
SRC0- 16. SRC0-15 inputs go through the routing control logic and get combined/routed to
any of the 13 internal IRQ lines. Interrupt input SRC16 is a special 8 bit wide input port in that
it bypasses the routing logic and is connected directly to the serialIRQ frame generator. SRC16
is provided so that 16550 UART interrupts can be handled in a way that's compatible with
legacy drivers.
The internal IRQ signals fall into three different categories: IRQ0-1 are routed to the serial IRQ
port and they have message FIFOs (discussed below). IRQ2-4 are routed to serial IRQ but
have no message FIFOs. IRQ5-8 bypass the serial IRQ and are routed to four discrete output
ports.
The first IRQ group (IRQ0-1) has a pair of message FIFOs. Upon detection of an interrupt
event, FPGA hardware pushes a message into the message FIFO and clears the status register.
The SERIRQ protocol is used to communicate the pending interrupt to the processor. Upon
notification, the processor reads the message FIFO to determine the interrupt source and does
not have to clear the status register. This interrupt mechanism minimizes the latency incurred
for interrupt processing.
The second IRQ group (IRQ2-4) is routed to the CPU using the SERIRQ protocol. These IRQs
do not have a message FIFO. The CPU must read the interrupt source register from the FPGA
and must clear the status.
The third group (IRQ5-8) is routed directly to PIRQx inputs of the PCH. Upon notification, the
CPU uses the PCI interrupt servicing method.
Interrupt Source
Grouping
The interrupt sources are grouped into 17 input busses. The first eight groups (SRC0-7) are
vectors of up to 32 interrupts each. The number of interrupts by group is defined by
parameters. The eight groups SRC8-15 are scalars and are composed of only one interrupt
each. Group SRC16 is a vector of up to eight interrupt inputs.
Interrupt Controller
SERIRQ I/F
TWO Interrupt Message
FIFO 32 word deep
Interrupt
Queue 2
Bus I/F to LPC Block
Addr/Data/Ctrl
SERIRQ
To PCH SERIRQ
To LPC Bus
Interrupt
Queue 1
Interrupt Enable, Routing, and Grouping
IRQ-0
IRQ-1
IRQ-2
SRC0
SRC8
PIRQ
IRQ-3 IRQ-4
SRC7
SRC15
n
n
IRQ
Mapping
reg
8
8
SRC16
IRQ-5:8
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