Hal Communications DKB-2010 Instruction Manual Download

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through an inverter to drive the gates at the inputs of the shift register stages high, allowing data from the
storage buffer to enter.

If the keyboard is in the RTTY mode, the

M/R

line is high, and the Q or "1" output of the first control flip-

flop (pin 9 of IC-7) passes through a NAND gate (part of IC-16) to drive the

RTTY LOAD

line low. This signal

is returned to the RTTY control circuit (Figure 8.5), where it sets the RTTY run flip-flop. The RTTY START
line, driven high by the RTTY run flip-flop output, is combined with the M/R bus in a NOR gate (IC-8), with

the result that the shift register reset bus is driven high, allowing the flip-flops to assume the states of the
incoming data lines.

Similarly, if the keyboard is in the Morse mode, the MORSE START signal, supplied from the Morse

character generator (Figure 8.10), goes high when the character generator is ready to accept data for a new
character, releasing the shift register reset terminals.

Once the character has been loaded into the register, it is ready to be clocked out to the RTTY loop

keying circuit or the Morse character generator, depending on the mode selected. Clock pulses are supplied
to the clock terminals of the register stages from either the RTTY control circuitry via the

RTTY SHIFT

line

or from the Morse character generator on the

MORSE SHIFT

line. In Morse mode, the

RTTY LOAD

line is

inhibited by the low input on the M/R bus connected to pin 2 of IC-16; hence, the RTTY run flip-flop is not

set at the beginning of a character, and the RTTY control circuit does not produce clock pulses. Conversely,
the Morse clock oscillator is inhibited during RTTY operation, so that the only clock pulses reaching the shift
register are those from the RTTY control circuit.

Each time a positive-going clock transition occurs, the contents of the register shift one stage of the

right. Consequently, the input data, which arrive at the register in parallel form, appear at the register
output bus (labeled SHIFT REGISTER) serially. From there the character code passes to the Morse character

generator and the RTTY encoder and loop interface. One or the other of these circuits is activated,

depending on the setting of the mode switch, and the desired Morse or RTTY output is produced.

The pattern of bits loaded into the shift register depends on the keyboard mode. Let us consider the

RTTY mode first. Each RTTY character code consists of seven pulses: a start pulse (always a space), five
select pulses which define the character, and a stop pulse (always a mark) which is about 50 per cent longer

than the other pulses.

The character code from the ROM code converter passes through the storage buffer and appears on data

lines D

through D

. Lines D

through D

define the character. As mentioned in Section 4.5, bit D

is used in

the RTTY mode to signal the case code circuit when a case change occurs. Hence, it is not loaded into the
shift register. Although it appears at one input of a NAND gate (pin 13 of IC-18) connected to the data input
of the first register stage, it is prevented from passing to the stage by the low level on the M/R bus, which is
tied to the other gate input. Consequently, the gate output remains high, and the first stage is set

unconditionally to the "1" state to produce the start pulse (a space).

Bits D

through D

are loaded into the second through sixth stages of the shift register when the

BUFFER

READ

line is low and the RTTY START bus goes high.

Bits D

and D

, like the D

bit, are used in the RTTY mode for control functions rather than as part of the

character code. They are also blocked from the shift register inputs by gates (part of IC-11). The high level
on the M/R bus holds the gate outputs low regardless of the levels on the D

and D

lines. As a result,

stages 7, 8 and 9 remain in the "0" state. The tenth stage is also left in the "0" state, since its data input is
grounded.

Once the input data have been loaded into the register flip-flops, the character timing counter becomes

active and clock pulses flow to the shift register. The frequency of the 0 clock signal supplied to the counter

is divided by two in the first counter flip-flop, so that the shift register is clocked at the proper baud rate for
the RTTY speed chosen.

Figure 4.2 illustrates the timing and register states for transmission of the character "F" (space-mark-

space-mark-mark-space-mark). Note that the stop pulse is the required 50 per cent longer than the other
select pulses.