5
Input Path .................................................................................................................................................................... 64
Input ranges................................................................................................................................................................. 64
Read out of input features .............................................................................................................................................. 65
Input termination........................................................................................................................................................... 66
Input coupling .............................................................................................................................................................. 66
AC/DC offset compensation .......................................................................................................................................... 66
Anti aliasing filter (Bandwidth limit)................................................................................................................................. 66
Enhanced Status Register ............................................................................................................................................... 67
Automatic on-board calibration of the offset and gain settings............................................................................................ 67
Card Status.................................................................................................................................................................. 69
Acquisition cards status overview ................................................................................................................................... 70
Generation card status overview .................................................................................................................................... 70
Data Transfer ............................................................................................................................................................... 70
Card mode .................................................................................................................................................................. 73
Length and Pretrigger.................................................................................................................................................... 73
Difference to standard single acquisition mode................................................................................................................. 74
Example FIFO acquisition .............................................................................................................................................. 74
Limits of pre trigger, post trigger, memory size ................................................................................................................. 74
Buffer handling .................................................................................................................................................................. 75
Data organisation .............................................................................................................................................................. 79
Sample format ................................................................................................................................................................... 79
Converting ADC samples to voltage values............................................................................................................................ 79
Standard internal sampling clock (PLL)............................................................................................................................. 81
Using Quartz2 with PLL (optional, M4i cards only)............................................................................................................ 81
External clock (reference clock) ...................................................................................................................................... 82
General Description............................................................................................................................................................ 83
Trigger Engine Overview..................................................................................................................................................... 83
Multi Purpose I/O Lines....................................................................................................................................................... 84
Programming the behaviour ........................................................................................................................................... 84
Using asynchronous I/O ............................................................................................................................................... 84
Special behaviour of trigger output ................................................................................................................................. 85
Special direct trigger output modes................................................................................................................................. 85
Trigger OR mask .......................................................................................................................................................... 86
Trigger AND mask........................................................................................................................................................ 87
Software trigger ................................................................................................................................................................. 88
Force- and Enable trigger .................................................................................................................................................... 88
Trigger delay ..................................................................................................................................................................... 89
External (analog) trigger ..................................................................................................................................................... 90
Trigger Mode............................................................................................................................................................... 90
Trigger Input Coupling .................................................................................................................................................. 91
Trigger level................................................................................................................................................................. 91
Detailed description of the external analog trigger modes ................................................................................................. 91
Overview of the channel trigger registers......................................................................................................................... 98
Channel trigger level..................................................................................................................................................... 99
Detailed description of the channel trigger modes........................................................................................................... 100