SERIES IP1K110 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com
http://www.acromag.com
Fail-Safe Operation
The IP1K110 operation is considered ‘Fail-safe’. That is, the
input/output channels are always configured as input upon power-
up reset, and a system software reset. This is done for safety
reasons to ensure reliable control of the output state under all
conditions.
Digital I/O Interface
The IP1K110 allows interface with a mix of up to 48 TTL I/O
channel or up to 24 differential I/O signals. The signals DIO0 to
DIO47 are utilized for digital input/output control to the field
signals. The six signals DIFF_DIR(1-6), given in Table 4.1,
control data direction of the 24 differential I/O signals. The six
signals TTL_DIR(1-6) control data direction of the 48 TTL I/O
channels.
EIA-RS485 AND RS422 SERIAL INTERFACE
The EIA-RS485 and RS422 interface specifies a balanced
driver with balanced receivers. Balanced data transmission
refers to the fact that two conductors are switched per signal and
the logical state of the data is referenced by the difference in
potential between the two conductors, not with respect to signal
ground. The differential method of data transmission makes EIA-
RS485 and RS422 ideal for noisy environments since it
minimizes the effects of coupled noise and ground potential
differences. That is, since these effects are seen as common-
mode voltages (common to both lines), not differential, they are
rejected by the receivers.
The EIA-RS422 standard defines a bus with a single driver
and multiple receivers.
The EIA-RS485 standard defines a bi-directional, terminated,
driver and receiver configuration. Half-duplex operation is
mandated by the sharing of a single data path for transmit and
receive. The maximum data transmission cable length is
generally limited to 4000 feet without a signal repeater installed.
With respect to EIA-RS485 and RS422, logic states are
represented by differential voltages from 1.5 to 5V. The polarity
of the differential voltage determines the logical state. A logic “0”
is represented by a negative differential voltage between the
terminals (measured A to B, or + to -). A logic “1” is represented
by a positive differential voltage between the terminals (measured
A to B, or + to -). The line receivers convert these signals to the
conventional TTL level.
Memory Interface
The IP1K110 interfaces to a 64K word SRAM device. This
memory interface utilizes the address signals RAMa1 to
RAMa16, data signals RAMd0 to RAMd15, and the read/write
control signals nWE_RAM, nBLE_RAM, nBHE_RAM, and
nOE_RAM as listed in Table 4.1. The RAM device is the
Integrated Device Technology IDT71016 or the Cypress
Cy7C1021.
IP Bus Interface
The IP1K110 interfaces to the carrier board per IP Module
specification ANSI/VITA 4 1995. The FPGA signals utilized are:
16 data lines (DATA0 to DATA15), and six address lines A(1 to
6). The many control lines that comprise the IP bus include: IP
Reset, nIOsel, nIDsel, nMEMsel, nINTsel, R_nW, nAck,
nIntReq0, nIntReq1, nDMAReq0, nDMAReq1, nDMAck,
nDMAend, nStrobe, nBS0, and nBS1. Table 4.1 lists the FPGA
pins corresponding to these signals. The IP bus 8MHz clock
signal is present on pin IP CLK. The function and timing
requirements of all IP bus signals are specified in the ANSI/VITA
4 1995 specification. Copies of the ANSI/VITA 4 1995
specification are available from VITA (www.vita.com).
Clock Generator Interface
A clock generator chip (Cypress CY22150) is available to
provide a user programmable clock frequency between 250KHz
and 100MHz. A total of four signals are utilized: Ref Clock,
SCLK, SDATA, and Gen Clock as seen in Table 4.1.
Signal
Description
Ref Clock
The Ref Clock or reference clock is a 8MHz
clock generated by the FPGA from the IP
carrier clock signal.
SCLK
This is the serial clock to the CY22150. It
is used for clock frequency programming.
SDATA
The serial data is sent from the FPGA to
the CY22150 on this pin for clock frequency
programming.
Gen Clock
The clock frequency generated by the
CY22150 is input to the FPGA on this pin.
Initialization Interface
The configuration method used by the IP1K110 is the Altera
passive parallel asynchronous. The initialization interface utilizes
eight signals. nConfig, Conf_Done, RDYnBUSY, Init_Done,
nStatus, nWS, CS, and nCS. The function and timing
requirements of these signals are defined by the Altera
Configuring Devices Application Note 116. A copy of the
Configuring Devices Application note 116 is available from Altera
(www.altera.com).
SIGNAL PIN ASSIGNMENTS
The signal pin assignments for the IP1K110 are listed in table
4.1. The pin assignments shown must be fixed in your Altera
ACF file. An example ACF file is provided with the design files
that accompany the IP1K110 EDK.
Table 4.1: Altera FPGA Pin Assignments
Pin
Signal
I/O
1
TCK
Input (Pull-Down)
2
Conf_Done
Output (2 CPLD)
3
nCEO
Output (Unconnect)
4
TDO
Output (Unconnect)
5
VCCIO
3.3Volts
6
GND
GND
7
RAMa1
Output
8
RAMa2
Output
9
RAMa3
Output
10
CLKUSR
Input (Pulled High)
