SERIES IP503 INDUSTRIAL I/O PACK EIA/TIA-232E & CENTRONICS COMMUNICATION MODULE
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Line Control Register continued
LCR Bit
FUNCTION
PROGRAMMING
6
Break Control
0 = Break Disabled
1 = Break Enabled
When break is enabled, the serial
output line (TxD) is forced to the
space state (low)This bit acts only
on the serial output and does not
affect transmitter logic. For
example, if the following sequence
is used, no invalid characters are
transmitted due to the presence of
the break
1Load a zero byte in response to
the Transmitter Holding Regis ter
Empty (THRE) status indication
2Set the break in response to the
next THRE status indication
3Wait for the transmitter to
become idle when the Transmitter
Empty status signal is set
high (TEMT=1); then clear the
break when normal transmission
has to be restored
7
Divisor Latch
Access Bit
0 = Access Receiver Buffer
1 = Allow Access to Divisor
Latches
Note that bit 7 must be set high to access the divisor latch
registers of the baud rate generator (DLL & DLM) during a
read/write operation. Bit 7 must be low to access the Receiver
Buffer Register (RBR), the Transmitter Holding Register (THR),
or the Interrupt-Enable Register (IER)A power-up or system reset
sets all LCR bits to 0
A detailed discussion of word length, stop bits, parity, and the
break signal is included in Section 40 (Theory of Operation)
MCR - Modem Control Register, Ports A & B (R/W)
The Modem Control register controls the interface with the
modem or data set as described below. The RTS and DTR
outputs are directly controlled by their control bits in this register
(a 1 bit asserts these signals at the output)
Modem Control Register
MCR Bit
FUNCTION
PROGRAMMING
0
Data Terminal
Ready Output
Signal (DTR)
0 = DTR* Not Asserted (Inactive)
1 = DTR* Asserted (Active)
1
Request to
Send Output
Signal (RTS)
0 = RTS* Not Asserted (Inactive)
1 = RTS* Asserted (Active)
2
Out1 (Internal)
No Effect on External Operation
3
Out2 (Internal)
0 = External Serial Channel
Interrupt Disabled
1 = External Serial Channel
Interrupt Enabled
4
Loop
1
0 = Loop Disabled
1 = Loop Enabled
5,6,7
Not Used
Bits are set to logic 0
Notes (Modem Control Register):
1 MCR Bit 4 provides a local loopback feature for diagnostic
testing of the UART channel. When set high, the UART
serial output (connected to the TXD driver) is set to the
marking (logic 1 state), and the UART receiver serial data
input is disconnected from the RxD receiver path. The output
of the UART transmitter shift register is then looped back into
the receiver shift register input. The four modem control
inputs (CTS,DSR, DCD, and RI) are disconnected from their
receiver input paths. The four modem control outputs (DTR,
RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs (while their associated pins are forced
to their high/ inactive state)Thus, in the loopback diagnostic
mode, transmitted data is immediately received permitting
the host processor to verify the transmit and receive data
paths of the selected serial channel. In this mode, interrupts
are generated by controlling the state of the four lower order
MCR bits internally, instead of by the external hardware
paths. However, no interrupt requests or interrupt vectors are
actually served in Loopback Mode, and interrupt pending
status isonly reflected internally
A power-up or system reset sets all MCR bits to 0 (bits 5-7
are permanently low)
LSR - Line Status Register, Ports A, B (Read/Write-
Restricted)
The Line Status Register (LSR) provides status indication
corresponding to the data transfer. LSR bits 1-4 are the error
conditions that produce receiver line-status interrupts (a priority 1
interrupt of the Interrupt Identification Register)The line status
register may be written, but this is intended for factory test and
should be considered read-only by the applications software
Line Status Register
LSR Bit
FUNCTION
PROGRAMMING
0
Data Ready
(DR)
0 = Not Ready (reset low by CPU
Read of RBR or FIFO)
1 = Data Ready (set high when a
character is received and transferred
into the RBR or FIFO)
1
Overrun
Error (OE)
0 = No Error
1 = Indicates that data in the RBR is
not being read before the next
character is transferred into the RBR,
overwriting the previous character. In
the FIFO mode, it is set after the
FIFO is filled and the next character
is received. The overrun error is
detected by the CPU on the first
LSR read after it happens. The
character in the shift register is not
transferred into the FIFO, but is
overwritten. This bit is reset low
when the CPU reads the LSR
