Pro II: Digital-I/O Modules
Pro II-CNT-x Rev. E
ADwin
140
ADwin-Pro II
Hardware, manual Dec. 2018
it can be used to clear or latch the counter (after release of the CLR or
LATCH input). The counter is cleared when the signalsA, B and CLR are
on logic "1" (software-selectable: clear, when only the CLR signal is on
logic "1").
PWM counter
The PWM counter of the counter block analyzes the signals at the PWM inputs.
You can set the input pin as well as the triggering edge with the instruction
P2_Cnt_Mode
.
Please note: On the module
Pro II-CNT-T
the PWM input pins A and B are tied
to four edge evaluation, the pins CLK and DIR to clock / direction evaluation.
Via standard instructions the following data can be read directly:
– frequency and duty cycle (with
P2_Cnt_Get_PW
)
– high and low time (with
P2_Cnt_Get_PW_HL
)
Exception:
evaluate PWM registers
on your own
There are several registers assigned to each PWM counter being described
below. If PWM counters are evaluated with standard instructions mentioned
above, no further knowledge is required about PWM registers. Use the evalu-
ation with PWM registers for special solutions only.
In order to evaluate PWM signals, the counter values of the current and the 2
preceding counter values are stored in latch registers, both for rising and falling
edges. In addition, there is a "shadow register" for each of these 6 registers:
the values of all 6 registers can at the same moment be copied to the 6 shadow
registers to be available for calculations.
The register values are changed with any edge like this:
– Rising edge:
• Copy counter value to L1+
• If rising edge is set as reference edge:
Copy register L2+ to L3+
Copy register L1+ to L2+
Copy register L2– to L3–
Copy register L1– to L2–
– Falling edge:
• Copy counter value to L1–
• If falling edge is set as reference edge:
Copy register L2– to L3–
Copy register L1– to L2–
Copy register L2+ to L3+
Copy register L1+ to L2+
In addition, there is a single latch register where the counter value is copied by
software (instruction
P2_Cnt_PW_Latch
).
Register
Latch
Shadow
register
Latch 1 for positive edges (current)
L1+
SL1+
Latch 2 for positive edges
L2+
SL2+
Latch 3 for positive edges
L3+
SL3+
Latch 1 for negative edges (current)
L1–
SL1–
Latch 2 for negative edges
L2–
SL2–
Latch 3 for negative edges
L3–
SL3–
