ADwin-Pro II
Hardware, manual Dec. 2018
35
Pro II: Multi-IO Modules
Pro II-MIO-4-ET1 Rev. E
ADwin
The decoder inputs are provided on the 25-pole D-Sub connector
Conn2
; pin
assignment see fig. 22.
Counter block
The module Pro II-MIO-4-ET1 Rev. E provides a configurable multi-purpose
counter block. The counter block contains two 32-bit counters: First an
up/down counter or four edge evaluation for connection of encoders. Second,
a PWM counter to evaluate high and low times, duty cycle, or frequency. Both
counters of a block can be operated in parallel.
The counter inputs run differential.
Up/down counter
The up/down counter of a block can be operated in 2 modes:
– Clock / direction (CLK and DIR signals)
A negative edge at the CLK input is the counting impulse for the 32-bit
counter. The DIR signal sets the counting direction, TTL high means a
count-up, TTL low means a count-down.
You can latch the counter values program-controlled or you can influ-
ence the counter by an external CLR/LATCH signal.
Depending on the programming the CLR/LATCH signal has either the
effect that the counter values are cleared (CLR) or that the counter val-
ues are latched (LATCH). This function will only be effective when it is
r e l e a s e d b y t h e i n s t r u c t i o n s
P 2 _ C N T _ C L E A R _ E N A B L E
o r
P2_CNT_LATCH_ENABLE
.
The counter is cleared or latched with a rising adge at input
CLR/LATCH. During the latch process the frequency of the measure-
ment can be determined by getting the difference of two read latch val-
ues, because this difference defines the number of pulses between the
two reading processes.
– Four edge evaluation (A and B signals)
The four edge evaluation changes the signals (which should be 90° pha-
se-shifted) of a connected incremental encoder at the inputs A and B to
CLK and DIR signals. For this you have to program the inputs corre-
spondingly (see "
ADwin-Pro
System Description, Programming in
AD-
basic
").
Since every edge of the A and B signals generates a count impulse, the
resolution is increased by factor 4. If the encoder has a reference signal,
it can be used to clear or latch the counter (after release of the CLR or
LATCH input). The counter is cleared when the signalsA, B and CLR are
on logic "1" (software-selectable: clear, when only the CLR signal is on
logic "1").
PWM Counter
The PWM counter of the counter block analyzes the signals at the PWM inputs.
Via software instructions the following data can be read directly:
– frequency and duty cycle (with
P2_Cnt_Get_PW
)
– high and low time (with
P2_Cnt_Get_PW_HL
)
The counter inputs are provided on the 25-pole D-Sub connector
Conn2
; pin
assignment see fig. 22.
If PWM counters are evaluated with standard instructions, no further knowl-
edge is required.
If you require other evaluation methods, you can use several registers
assigned to each PWM counter to create a solution. You find a description of
PWM registers on page 140 (module Pro II-CNT-x Rev. E). Use the evaluation
with PWM registers for special solutions only.
