229
8-4. Table of Special Data Registers
Note:
• C24C, C40C, C56C, and C72C types only.
A: Available, N/A: Not available
Address
Name
Description
Availability
C14/
C16
C24/
C40
C56/
C72
DT9058
DT9059
DT9060
DT9061
DT9062
DT9063
DT9064
DT9065
DT9066
DT9067
Clock/calendar
adjustment register
Communication
error code register
•
•
•
•
•
The clock/calendar is adjusted as follows when the
least significant bit of DT9058 is set to “1”.
- When second data is H00 to H29 (BCD),
the second data is cut off to H00 (BCD).
- When second data is H30 to H59 (BCD),
the second data is cut off to H00 (BCD) and one
is added to the minute data.
The revised clock/calendar settings, which are
performed using
F0 (MV)
instructions, become
effective when the most significant bit of DT9058
is set to “1”.
An RS232C port communication error code is
stored in the higher 8-bit area of DT9059.
A programming tools port communication error
code is stored in the lower 8-bit area of DT9059.
These registers monitor the condition of step
ladder programs.
Execution of the step ladder program is monitored
as follows:
- Executing:
- Not executing:
<EXAMPLE>
Each bit in the registers corresponds to a step
ladder process as shown in the following example:
When bit position 0 of DT9061 is “1”, step
ladder process 16 is executing.
1
0
Bit position
Process number
DT9061
0 0 0 0
11
8
3
0
15
•
•
12
•
•
•
•
7
4
•
•
0 0 0 0 0 0 0 0 0 0 0 1
27
24
19
16
31
•
•
28
•
•
•
•
23
20
•
•
Process
number:
0 to 15
Process
number:
16 to 31
Process
number:
32 to 47
Process
number:
48 to 63
Process
number:
64 to 79
Process
number:
80 to 95
Process
number:
96 to 111
Process
number:
112 to 127
Step
ladder
process
monitor
registers
A
(See note.)
N/A
A
Summary of Contents for FP1
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