Register
Bit Number
Function Addre
ss
Name
R/W
7 6 5 4 3 2 1 0
Logic
Default Description
ABh
*5
RUN_
EVT_STS
R/W
0x00
ACh
*5
WAKE_
EVT_STS
R/W
B
T
P
2
S
M
B
A
L
R
T
G
P
I
O
R
E
S
B
A
T
2
B
A
T
1
A
D
P
Read
0:No event
1:EVT detection
Write
0:Clear event
1:Ignore
0x00
BTP2 =1:
SMB =1 :
ALRT=1 :
GPIO =1 :
BATn=1 :
ADP =1 :
TH =1 :
HIGH=1 :
LOW =1 :
ERR =1 :
BTP2 event
is detected
SMBus event
is detected.
SMBAlert is
detected.
GPIO event
is detected.
Battery event
is detected.
Battery event
is detected.
Thermal
event is
detected
High alarm
point is
detected.
Low alarm
point is
detected.
Polling
communicati
on failure
with retry.
ADh
*5
RUN_
EVT_STS_2
R/W
Reserved [7:1]
T
H
0x00
AEh
*5
WAKE
EVT_STS_2
R/W
Reserved [7:1]
T
H
0x00
AFh
*5
THERMAL_
EVT_STS
R/W
Reserved [7:3]
E
R
R
L
O
W
H
I
G
H
0x00
To clear the notified event
flag without unexpected
event loss, clear the
corresponding bit flag only.
For this operation, this
register has special writing
manner as follows.
STS_X
ß
(STS_X)
AND (Written data)
B0h
EC_RUN_
ENB
R/W
0: Disable
1: Enable
0x00
B1h
EC_WAKE_
ENB
R/W
B
T
P
2
S
M
B
A
L
R
T
RES[4:1]
A
D
P 0: Disable
1: Enable
0x00
BTP2:
SMB :
ALRT:
ADP:
BTP2 event
SMBus event.
SMBAlert event.
Adapter event.
B2h
BATT_RUN
_
ENB
R/W
0: Disable
1: Enable
0x00
B3h
BATT_WA
KE
_ENB
R/W
B
T
P
E
M
P
L
O
W
W
A
R
E
R
R
C
A
P
C
/
D
C
O
N 0: Disable
1: Enable
0x00
BTP:
EMP:
LOW:
WAR:
ERR:
CAP:
C/D:
CON:
Battery trip point
Empty.
Low battery
Warning
Error
Capacity learning
Charge/Discharge
Battery presence
B4h
GPIO-A_
IO_CONF
R/W
CONF_A [7:0]
0: Input
1: Output
0x00
B5h
GPIO-A_
DATA
R/W
DATA_A [7:0]
-
B6h
GPIO-A_
RUN_ENB
R/W
RUN_ENB_A [7:0]
0: Disable
1: Enable
0x00
Event/
GPIO
Control
B7h
GPIO-A_
EVT_POL
R/W
POL_A [7:0]
0: Falling edge
1: Rising edge
0x00
For detail information, refer
to GPIO section in this
document.
TECHNICAL SERVICE MANUAL
Prestigio Cavaliere 142
57
