SERIES IP330 INDUSTRIAL I/O PACK 16-BIT HIGH DENSITY ANALOG INPUT MODULE
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Programming Interrupts
Interrupts can be enabled for generation after conversion of
individual channels or after a group of channels have been
converted. Interrupts generated by the IP330 use interrupt request
line INTREQ0* (Interrupt Request 0). The interrupt release
mechanism is Release On Acknowledge (ROAK) type. That is,
the IP330 will release the INTREQ0* signal during an interrupt
acknowledge cycle from the carrier.
The IP330 Interrupt Vector register can be used as a pointer to
an interrupt handling routine. The vector is an 8-bit value and can
be used to point to any one of 256 possible locations to access the
interrupt handling routine.
This example assumes that the IP330 is installed onto an
Acromag AVME9630/60 carrier board (consult your carrier board
documentation for compatibility details).
Interrupt Programming Example with AVME9630/60 Carrier
1.
Clear the global interrupt enable bit in the carrier board status
register by writing a “0” to bit 3.
2.
Write the interrupt vector to the IP330 Module at base
a 03H.
3.
Write to the carrier board interrupt Level Register to program
the desired interrupt level per bits 2,1, & 0.
4.
Write “1” to the carrier board IP Interrupt Clear Register
corresponding to the desired IP interrupt request being
configured.
5.
Write “1” to the carrier board IP Interrupt Enable Register bit
corresponding to the IP interrupt request to be enabled.
6.
Enable interrupts for the carrier board by writing a “1” to bit 3
(the Global Interrupt Enable Bit) of the carrier board’s Status
Register.
7.
Enable the IP330 for interrupt after each channel or after
conversion of a group of channels by setting bits 12 and 13 of
the Control register as required.
8.
Interrupts can now be generated after start of a scan mode of
operation (burst, continuous, or external trigger only).
General Sequence of Events for Processing an Interrupt
1.
The IP330 asserts the Interrupt Request 0 Line (INTREQ0*)
in response to an interrupt condition.
2.
The AVME9630/60 carrier board acts as an interrupter in
making the VMEbus interrupt request (IRQx*) corresponding
to the IP interrupt request.
3.
The VMEbus host (interrupt handler) asserts IACK* and the
level of the interrupt it is seeking on A01-A03.
4.
When the asserted VMEbus IACKIN* signal (daisy-chained)
is passed to the AVME9630/60, the carrier board will check if
the level requested matches that specified by the host. If it
matches, carrier board will assert the INTSEL* line to the
appropriate IP together with (carrier board generated)
address bit A1 to select which interrupt request is being
processed (A1 low corresponds to INTREQ0*).
5.
The IP330 puts the interrupt vector on the local data bus
(D00-D07 for the D08 [O] interrupter) and asserts ACK* to the
carrier board. The carrier board passes this along to the
VMEbus (D08[O]) and asserts DTACK*.
6.
The host uses the vector to form a pointer to an interrupt
service routine for the interrupt handler to begin execution.
7.
Example of Generic Interrupt Handler Actions:
a) Disable the interrupting IP by writing “0” to the
appropriate bit in the AVME9630/60 IP Interrupt Enable
Register.
b) Service the interrupt by reading converted data resident
in the Mail Box buffer of the IP330. Use the New Data
Available register to identify valid Mail Box Buffer data.
c)
Clear the interrupting IP by writing a “1” to the
appropriate bit in the AVME9630/60 IP Interrupt Clear
register.
d) Enable the interrupting IP by writing “1” to the
appropriate bit in the AVME9630/60 IP Interrupt Enable
Register.
4.0 THEORY OF OPERATION
This section contains information regarding the hardware of
the IP330. A description of the basic functionality of the circuitry
used on the board is also provided. Refer to the Block Diagram
shown in Drawing 4501-592 as you review this material.
FIELD ANALOG INPUTS
The field I/O interface to the carrier board is provided through
connector P2 (refer to Table 2.3).
Field I/O signals are NON-
ISOLATED.
This means that the field return and logic common
have a direct electrical connection to each other. As such, care
must be taken to avoid ground loops (see Section 2 for connection
recommendations). Ignoring this effect may cause operation
errors, and with extreme abuse, possible circuit damage. Refer to
Drawing 4501-591 for example wiring and grounding connections.
Analog inputs and calibration voltages are selected via analog
multiplexers. IP330 control logic automatically programs the
multiplexers for selection of the required analog input channel.
The multiplexer control is based upon selection of single ended or
differential analog input and the Start and End channel register
values.
Single ended and differential channels cannot be mixed (i.e.
they must all be single ended or differentially wired). Up to 32
single ended inputs can be monitored, where each channel’s +
input is individually selected along with a single sense lead for all
channels. Up to 16 differential inputs can be monitored, where
each channel’s + and - inputs are individually selected.
A Programmable Gain (Instrumentation) Amplifier (PGA) takes
as input the selected channel’s + and - inputs (or + and sense) and
outputs a single ended voltage proportional to it. The gain can be
1, 2, 4, or 8 and is selected through the Gain Control registers.
The output of the PGA feeds the A/D (Analog to Digital)
Converter. The A/D Converter is a state of the art, 16-bit,
successive approximation converter with a built-in sample and hold
circuit. The sample and hold circuit goes into the hold mode when
a conversion is initiated. This maintains the selected channel’s
voltage constant until the A/D has accurately digitized the input.
Then it returns to sample mode to acquire the next channel. Once
a conversion has been started, control logic on the IP330
automatically updates the multiplexer and PGA for the next
channel to be converted as required. This allows the input to
settle for the next channel while the previous channel is
converting. This pipelined mode of operation facilitates a
maximum system throughput.
