SERIES IP330 INDUSTRIAL I/O PACK 16-BIT HIGH DENSITY ANALOG INPUT MODULE
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Uniform Single-Mode
In uniform single mode of operation, conversions are
performed once (in sequential order) for all channels between and
including the Start and End Channel Values. The interval between
conversions is controlled by the interval timer (Timer Prescaler and
Conversion Timer as described in the Conversion Timer Register
section). The interval timer must be used in this mode of
operation.
After software selection of the uniform single mode of
operation, conversions are started either by an external trigger, or
by setting the software start convert bit. If the external trigger is to
be used bit-2 of the Control register must be set low to accept the
external trigger as an input signal.
When configured for differential input, the Mail Box functions
as a dual level data buffer. However, for Uniform Single Mode,
only one pass from the start channel to the end channel is
implemented. Thus, only the first half of the Mail Box buffer is
utilized. As seen in Table 3.2, the first half of the Mail Box is
defined by word addresses 40H to 5EH
Interrupts can be enabled to activate after conversion of each
channel or the group of channels as defined by the Start and End
Channel Values. If interrupts are configured to go active after the
conversion of each channel, the actual interrupt will be issued 8
µ
seconds after the programmed interval has lapsed. If interrupt
upon completion of a group of channels is selected, an interrupt
will be issued 8
µ
seconds after the interval time of the last
selected channel has expired.
Burst Continuous-Mode
In burst continuous mode of operation, conversions are
continuously performed in sequential order from the channel
defined by the Start Channel Value to the channel defined by the
End Channel Value. Within a group of channels, the interval
between conversions is fixed at 15
µ
seconds. However the
interval after conversion of a group of channels can be controlled
by the interval timer (Timer Prescaler and Conversion Timer).
Burst modes can be used to provide pseudo-simultaneous
sampling for may low to medium speed applications requiring
simultaneous channel acquisition. The 15
µ
seconds between
conversion of each channel can essentially be considered
simultaneous sampling for low to medium frequency applications.
After software selection of the burst continuous mode of
operation, conversions are started either by an external trigger, or
by setting the software start convert bit. If the external trigger is to
be used bit-2 of the Control register must be set low to accept the
external trigger as an input signal.
Stopping the execution of burst continuous conversions is
accomplished by writing 000 to the Scan Mode bits (8-10) of the
Control register. See the Control register section for additional
information on the Scan Mode control bits and the Control register
board address location.
When configured for differential input, the Mail Box functions
as a dual level data buffer. The first half of the Mail Box is used to
store all selected channel data for the initial pass through the
channels defined by the Start and End Value registers. The
second half of the Mail Box is then used to store the channel data
corresponding to the second pass though all selected channels.
Storage of channel data continues to alternate between the first
and second halves of the Mail Box Buffer. As seen in Table 3.2,
the first half of the Mail Box is defined by word addresses 40H to
5EH while the second half is defined by word addresses 60H to
7EH.
Interrupts can be enabled to activate after conversion of each
channel or the group of channels as defined by the Start and End
Channel Values. If interrupts are configured to go active after the
conversion of each channel, the actual interrupt will be issued
every 15
µ
seconds. If interrupt upon completion of a group of
channels is selected, an interrupt will be issued 23
µ
seconds after
conversion of the last channel in the group has started.
At this time 15
µ
seconds between interrupts is not sufficient time
to perform back to back interrupt acknowledge cycles on the VME
and PC platforms. Thus, interrupting after each channel is
converted cannot be recommended.
Burst Single-Mode
In burst single mode of operation conversions are performed
once for all channels (in sequential order) starting with Start
Channel and ending with the End Channel. The interval between
conversions of each channel is fixed at 15
µ
seconds. The interval
timer has no functionality in this mode of operation.
After software selection of the burst single mode of operation,
conversions are started either by an external trigger, or by setting
the software start convert bit. If the external trigger is to be used
bit-2 of the Control register must be set low to accept the external
trigger as an input signal.
When configured for differential input, the Mail Box functions
as a dual level data buffer. However, for Burst Single Mode, only
one pass from the start channel to the end channel is
implemented. Thus, only the first half of the Mail Box buffer is
utilized. As seen in Table 3.2, the first half of the Mail Box is
defined by word addresses 40H to 5EH.
Interrupts can be enabled to activate after conversion of each
channel or the group of channels as defined by the Start and End
Channel Values. If interrupts are configured to go active after the
conversion of each channel, an interrupt will be issued every 15
µ
seconds (not recommended). If interrupt upon completion of a
group of channels is selected, an interrupt will be issued 23
µ
seconds after conversion of the last channel has started.
Convert On External Trigger Only-Mode
In convert on External Trigger Only Mode of operation each
conversion is initiated by an external trigger (falling edge of a logic
low pulse) input to the IP330 on the EXT TRIGGER* signal of the
P2 connector. Conversions are performed for each channel
between and including the Start and End Channel Values in
sequential order. The interval between conversions is controlled
by the period between external triggers. The interval timer has no
functionality in this mode of operation and must be disabled by
setting bit-11 of the control register to logic low.
