SERIES IP330 INDUSTRIAL I/O PACK 16-BIT HIGH DENSITY ANALOG INPUT MODULE
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A miniature DIP switch on the board controls the range
selection for the A/D Converter (-5 to +5, -10 to +10, 0 to 5, and 0
to 10 Volts) as detailed in section 2. DIP switch selection should
be made prior to powering the unit. Thus, all channels will use the
same A/D Converter range. However, the analog input range can
vary on an individual channel basis depending on the
programmable gain selection.
The logic interface pr/- 12 Volt supplies to the analog
circuitry. The -10 to +10 and 0 to +10 Volt A/D Converter ranges
will be clipped if these supplies are used, typically to +/-8.5 Volt
maximum inputs. The user has the option of pro/- 15 Volt
external supplies to fully utilize input ranges to +/- 10 Volts. These
supplies are selected via hardware jumpers J1 and J2 as detailed
in section 2. Jumper selection should be made prior to powering
the unit. Internal and external supplies should not be mixed (e.g.
do not use +12 Volts with -15 Volts). When selecting supplies low
noise linears are preferred. All supplies should switch ON or OFF
at the same time.
The board contains four precision voltage references and a
ground (autozero) reference for use in calibration. These provide
considerable flexibility in obtaining accurate calibration for the
desired A/D Converter range and gain combination, when
compared to fixed hardware potentiometers for offset and gain
calibration of the A/D Converter and PGA.
LOGIC/POWER INTERFACE
The logic interface to the carrier board is made through
connector P1 (refer to Table 2.4). The P1 interface also provides
+5V and
±
12V power to the module. Note that the DMA control,
INTREQ1
∗
, ERROR
∗
, and STROBE
∗
signals are not used.
A Field Programmable Gate-Array (FPGA) installed on the IP
Module provides an interface to the carrier board per IP Module
specification revision 0.7.1. The interface to the carrier board
allows complete control of all IP330 functions.
IP INTERFACE LOGIC
IP interface logic of the IP330 is imbedded within the FPGA.
This logic includes: address decoding, I/O and ID read/write
control circuitry, and ID PROM implementation.
Address decoding of the six IP address signals A(1:6) is
implemented in the FPGA, in conjunction with the IP select
signals, to identify access to the IP modules ID or I/O space. In
addition, the byte strobes BS0
∗
and BS1
∗
are decoded to identify
low byte, high byte, or double byte data transfers.
The carrier to IP module interface implements access to both
ID and I/O space via 16 or 8-bit data transfers. Read only access
to ID space provides the identification for the individual module (as
given in Table 3.1) per the IP specification. Read and write
accesses to the I/O space provide a means to control the IP330
and retrieve newly converted data from the Mail Box buffer.
Access to both ID and I/O spaces are implemented with one
wait state read or write data transfers. There is one exception, on
a rare occasions read and write operations to the Mail Box buffer
may contend. Since the Mail Box buffer is not implemented as a
dual port memory, simultaneous read and write access to RAM is
not possible. If a read access to the RAM is initiated
simultaneously with an internal RAM write (for update of the Mail
Box buffer with ADC data), the read access will be held until after
the write operation has completed. Thus, the read operation from
RAM (Mail Box) may require up to six waits to avoid contention
with an internal write cycle.
IP330 CONTROL LOGIC
All logic to control data acquisition is imbedded in the IP’s
FPGA. The control logic of the IP330 is responsible for controlling
the operation of a user specified sequence of data acquisitions.
Once the IP330 has been configured, the control logic performs
the following:
•
Controls the channel multiplexers based upon start and
end channel values, and single ended or differential
analog input mode.
•
Selects channel gain at the programmable gain amplifier
corresponding to the current channel.
•
Controls data conversion at the A/D Converter based on
one of five different scan modes of operation.
•
Controls data transfer from the A/D Converter to the
FPGA’s 16-bit serial shift register.
•
Controls and updates the Mail Box buffer, New Data
register, and Missed Data register.
•
Stops data acquisition for Single Cycle Scan modes.
•
Provides external or internal trigger control.
•
Controls the interval between data conversions.
•
Issues interrupt requests to the carrier.
INTERNAL CHANNEL POINTERS
Internal counters in the FPGA are used as pointers to: control
the multiplexers for selection of the current channel’s analog
signal; select and set the current channel’s Gain; and control
update of the Mail Box RAM buffer. The start channel register
controls the value at which these counters start and the end value
register controls the maximum channel number which is reached.
In the continuous modes of operation these counters
continuously cycle, in sequential order, from the defined start value
to the defined end value. When the continuous mode of operation
is halted by disabling the scan mode via the control register, the
internal hardware counter remains at the count value reached
when halted. Upon start of a new scan mode, via the software
start convert bit or external trigger, the internal pointers are
reinitialized. Thus, the first channel converted, upon restart of data
conversions, will correspond to that set in the start value register.
A 16-bit serial shift register is implemented in the IP’s FPGA.
This serial shift register interfaces to the A/D Converter. A clock
signal provided by the converter is used to serially shift the new
data from the converter to the FPGA’s 16-bit serial shift register.
Use of the converter’s clock signal (instead of an external clock)
minimizes the danger of digital noise feeding through and
corrupting the results of a conversion in process.
