Data Sheet
111
Rev. 1.00
2017-07-31
TLE9262BQXV33
Supervision Functions
15.2.3
Watchdog Setting Check Sum
A check sum bit is part of the SPI commend to trigger the watchdog and to set the watchdog setting.
The sum of the 8 data bits in the register WWD_CTRL needs to have even parity (see
Equation (15.1)
). This is
realized by either setting the bit
CHECKSUM
to 0 or 1. If the check sum is wrong, then the SPI command is
ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set.
The checksum is calculated by taking all 8 data bits into account. The written value of the reserved bit 3 of the
WWD_CTRL register is considered (even if read as ‘0’ in the SPI output) for checksum calculation, i.e. if a 1 is
written on the reserved bit position, then a 1 will be used in the checksum calculation.
(15.1)
CHKSUM
Bit15
…
Bit8
⊕
⊕
=
