4.175
Date Code 20170814
Instruction Manual
SEL-700G Relay
Protection and Logic Functions
Group Settings (SET Command)
Figure 4.116
Simplified Block Diagram, Frequency and Phase Matching Elements
SEL-700G autosynchronism adjusts the generator frequency to match the
frequency of the system. The relay compares generator frequency to that of
the system/bus and asserts a Relay Word bit FRAISE or FLOWER, as
necessary.
The FRAISE and FLOWER bits provide correction pulses to facilitate
frequency matching. You must assign these bits to the necessary outputs (for
example, OUT301 etc., see Table 4.61 for detail) connected to the governor to
control the generator speed/frequency.
As shown in Figure 4.116, the relay computes the width of each correction
pulse, which is proportional to how far the slip is from the target slip
frequency. Set FADJRATE equal to the governor's rate of response to the
control pulses. Also set FPLSMIND and FPLSMAXD to define the minimum
and maximum limits of the computed pulse widths.
Set FPULSEI to define an interval for the FRAISE and FLOWER pulses.
Make sure that the interval setting is greater than the time necessary for the
generator frequency to stabilize after a control pulse is applied. This prevents
a premature application of the next control pulse from overshooting the target
slip. Refer to the governor data sheet for the information to properly set the
FADJRATE, FPLSMIND, FPLSMAXD, and FPULSEI settings.
As the slip frequency gets closer to the target slip, the correction pulses get
shorter to prevent hunting and stop when the slip frequency is within an
acceptable window (25SLO < SLIP < 25SHI). Typically, this creates an
acceptable slip condition that allows the synchronism-check function to assert
Relay Word bit 25C and initiate generator breaker closing.
Logic Activation
Activate
De-activate
(Higher Priority)
Relay
Word
Bit
Relay
Word
Bits
FSYNCT
1
sec
Measured
Frequencies
FREQX
(Gen. Frequency)
FREQS
(System Frequency)
AST
FSYNCST
FSYNCACT
FSYNCTO
FRAISE
FLOWER
Note: The logic is enabled when settngs E25X := YES and EAUTO := DIG.
The logic is de-activated and disabled when any of the following is true:
• Relay Word bit ASP, 52AX, TRIPX, BSYNCHX, or FSYNCTO is asserted.
• Relay Word bit 59VSX is deasserted.
• Both Relay Word bit FREQTRKX and ZCFREQX are deasserted.
Pulse Definition Processing
(Pulse width = 0 except as computed below)
SLIP = FREQX — FREQS
If (SLIP
>
25SHI) or (SLIP
<
25SLO):
Target Slip = (25SLO + 25SHI) / 2
Pulse Width
q
= |SLIP
−
Target Slip| / FADJRATE
Pulse Interval = FPULSEI
If 25SLO
≤
SLIP
≤
25SHI and |SLIP|
<
0.02 Hz:
Pulse Width
w
= |(0.02
−
|SLIP|)| / FADJRATE
Pulse Interval = KPULSEI
q
FPLSMIND
≤
Pulse Width
≤
FPLSMAXD
w
KPLSMIND
≤
Pulse Width
≤
KPLSMAXD
Pulse
Generator
SLIP
<
25SLO
SLIP
>
25SHI
See Note
Pulse Width
Pulse Interval
Pulse Width
Pulse Interval
Setting
Summary of Contents for SEL-700G Series
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