17.3.9 Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the last PCA module (module 5). The WDT is used to generate a
reset if the time between writes to the WDT update register (PCA0CPH5) exceed a specified limit. The WDT can be configured and
enabled/disabled as needed by software. With the WDTE bit set in the PCA0MD register, the last module operates as a watchdog timer
(WDT). The module 5 high byte is compared to the PCA counter high byte; the module 5 low byte holds the offset to be used when
WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some PCA registers are restricted while the Watch-
dog Timer is enabled. The WDT will generate a reset shortly after code begins execution. To avoid this reset, the WDT should be ex-
plicitly disabled (and optionally re-configured and re-enabled if it is used in the system).
Watchdog Timer Operation
While the WDT is enabled:
• PCA counter is forced on.
• Writes to PCA0L and PCA0H are not allowed.
• PCA clock source CPS field is frozen.
• PCA Idle control bit (CIDL) is frozen.
• Module 5 is forced into software timer mode.
• Writes to the Module 5 mode register (PCA0CPM5) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run until the WDT is disabled.
The PCA counter run control bit (CR) will read zero if the WDT is enabled but user software has not enabled the PCA counter. If a
match occurs between PCA0CPH5 and PCA0H while the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT
may be updated with a write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is loaded
into PCA0CPH5.
WDTE (Watchdog Enable)
8-bit
Comparator
match
Reset
Watchdog
PCA0CPHn
WDLCK (Watchdog Lock)
PCA0H
PCA0L overflow
8-bit Adder
Adder
Enable
Watchdog
PCA0CPLn
Write to Watchdog
PCA0CPHn
Figure 17.8. PCA Module 5 with Watchdog Timer Enabled
The 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L
overflows before a reset. Up to 256 PCA clocks may pass before the first PCA0L overflow occurs, depending on the value of the
PCA0L when the update is performed. The total offset is then given by the following equation in PCA clocks:
Offset = (256 ×
PCA
0
CPL
) + (256 –
PCA
0
L
)
Note:
PCA0L is the value of the PCA0L register at the time of the update in this equation.
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and PCA0H. Software may force a
WDT reset by writing a 1 to the CCF5 flag in the PCA0CN0 register while the WDT is enabled.
EFM8SB2 Reference Manual
Programmable Counter Array (PCA0)
silabs.com
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