18.3.5 Timing
The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and
hold time requirements. The Address Setup time, Address Hold time, RDb and WRb strobe widths, and in multiplexed mode, the width
of the ALE pulse are all programmable in units of SYSCLK periods.
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the
EMIF registers. Assuming non-multiplexed operation, the minimum execution time for an off-chip XRAM operation is 5 SYSCLK cycles
(1 SYSCLK for RDb or WRb pulse + 4 SYSCLKs). For multiplexed operations, the Address Latch Enable signal will require a minimum
of 2 additional SYSCLK cycles. Therefore, the minimum execution time of an off-chip XRAM operation in multiplexed mode is 7
SYSCLK cycles (2 SYSCLKs for ALEm, 1 for RDb or WRb + 4 SYSCLKs). The programmable setup and hold times default to the maxi-
mum delay settings after a reset.
Table 18.2. External Memory Interface Timing
Parameter
Description
Min
Max
Units
T
ACS
Address/Control Setup Time
0
3 x T
SYSCLK
ns
T
ACW
Address/Control Pulse Width
1 x T
SYSCLK
16 x T
SYSCLK
ns
T
ACH
Address/Control Hold Time
0
3 x T
SYSCLK
ns
T
ALEH
Address Latch Enable High Time
1 x T
SYSCLK
4 x T
SYSCLK
ns
T
ALEL
Address Latch Enable Low Time
1 x T
SYSCLK
4 x T
SYSCLK
ns
T
WDS
Write Data Setup Time
1 x T
SYSCLK
19 x T
SYSCLK
ns
T
WDH
Write Data Hold Time
0
3 x T
SYSCLK
ns
T
RDS
Read Data Setup Time
20
—
ns
T
RDH
Read Data Hold Time
0
—
ns
Note:
T
SYSCLK
is equal to one period of the device system clock (SYSCLK).
EFM8SB2 Reference Manual
External Memory Interface (EMIF0)
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