22.3.3 Data Transfer
UART0 provides standard asynchronous, full duplex communication. All data sent or received goes through the SBUF0 register and (in
9-bit mode) the RB8 bit in the SCON0 register.
Transmitting Data
Data transmission is initiated when software writes a data byte to the SBUF0 register. If 9-bit mode is used, software should set up the
desired 9th bit in TB8 prior to writing SBUF0. Data is transmitted LSB first from the TX pin. The TI flag in SCON0 is set at the end of the
transmission (at the beginning of the stop-bit time). If TI interrupts are enabled, TI will trigger an interrupt.
Receiving Data
To enable data reception, firmware should write the REN bit to 1. Data reception begins when a start condition is recognized on the RX
pin. Data will be received at the selected baud rate through the end of the data phase. Data will be transferred into the receive buffer
under the following conditions:
• There is room in the receive buffer for the data.
• MCE is set to 1 and the stop bit is also 1 (8-bit mode).
• MCE is set to 1 and the 9th bit is also 1 (9-bit mode).
• MCE is 0 (stop or 9th bit will be ignored).
In the event that there is not room in the receive buffer for the data, the most recently received data will be lost. The RI flag will be set
any time that valid data has been pushed into the receive buffer. If RI interrupts are enabled, RI will trigger an interrupt. Firmware may
read the 8 LSBs of received data by reading the SBUF0 register. The RB8 bit in SCON0 will represent the 9th received bit (in 9-bit
mode) or the stop bit (in 8-bit mode), and should be read prior to reading SBUF0.
22.3.4 Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special
use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the
target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE bit of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt
only if the ninth bit is logic 1 (RB8 = 1) signifying an address byte has been received. In the UART interrupt handler, software will com-
pare the received address with the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE bits set and do not generate
interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed
slave resets its MCE bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling
"broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions
or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between
the original master and slave(s).
Master
Device
Slave
Device
TX
RX
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
V+
Figure 22.5. Multi-Processor Mode Interconnect Diagram
EFM8SB2 Reference Manual
Universal Asynchronous Receiver/Transmitter 0 (UART0)
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