18.3 Functional Description
18.3.1 Overview
The devices include RAM mapped into the external data memory space (XRAM). Devices with enough pins also have an External
Memory Interface (EMIF0) which can be used to access off-chip memories and memory-mapped devices connected to the GPIO ports.
The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in either
the data pointer (DPTR), or with the target address low byte in R0 or R1 and the target address high byte in the External Memory Inter-
face Control Register (EMI0CN).
When using the MOVX instruction to access on-chip RAM, no additional initialization is required, and the MOVX instruction execution
time is as specified in the core chapter. When using the MOVX instruction to access off-chip RAM or memory-mapped devices, both the
Port I/O and EMIF should be configured for communication with external devices, and MOVX instruction timing is based on the value
programmed in the Timing Control Register (EMI0TC).
Configuring the External Memory Interface for off-chip memory space access consists of four steps:
1. Configure the output modes of the associated port pins as either push-pull or open-drain (push-pull is most common) and skip the
associated pins in the Crossbar (if necessary).
2. Configure port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or off-chip only).
4. Set up timing to interface with off-chip memory or peripherals.
18.3.2 Port I/O Configuration
When the External Memory Interface is used for off-chip access, the associated port pins are shared between the EMIF and the GPIO
port latches. The Crossbar should be configured not to assign any signals to the associated port pins. In most configurations, the RDb,
WRb, and ALEm pins need to be skipped in the Crossbar to ensure they are controlled by their port latches.
The External Memory Interface claims the associated port pins for memory operations only during the execution of an off-chip MOVX
instruction. Once the MOVX instruction has completed, control of the Port pins reverts to the Port latches. The Port latches should be
explicitly configured to “park” the External Memory Interface pins in a dormant state, most commonly by setting them to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the drivers on all port pins that are
acting as inputs (Data[7:0] during a Read operation, for example). For port pins acting as outputs (Data[7:0] during a Write operation,
for example), the External Memory Interface will not automatically enable the output driver. The output mode (whether the pin is config-
ured as open-drain or push-pull) of bi-directional and output only pins should be configured to the desired mode when the pin is being
used as an output.
The output mode of the port pins while controlled by the GPIO latch is unaffected by the External Memory Interface operation and re-
mains controlled by the PnMDOUT registers. In most cases, the output modes of all EMIF pins should be configured for push-pull
mode.
18.3.2.1 EMIF Pin Mapping
Table 18.1. EMIF Pin Mapping
Multiplexed EMIF Sig-
nal Name
Description
QFP32 Pin Name
QFN32 Pin Name
QFN24 Pin Name
WRb
Write Enable
P2.6
P2.6
Not Available
RDb
Read Enable
P2.5
P2.5
Not Available
ALEm
Address Latch Enable
P2.4
P2.4
Not Available
AD0m
Address/Data Bit 0
P1.0
P1.0
Not Available
AD1m
Address/Data Bit 1
P1.1
P1.1
Not Available
AD2m
Address/Data Bit 2
P1.2
P1.2
Not Available
AD3m
Address/Data Bit 3
P1.3
P1.3
Not Available
AD4m
Address/Data Bit 4
P1.4
P1.4
Not Available
EFM8SB2 Reference Manual
External Memory Interface (EMIF0)
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