19.3.4 Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPInCFG register. The CKPHA
bit selects one of two clock phases (edge used to latch the data). The CKPOL bit selects between an active-high or active-low clock.
Both master and slave devices must be configured to use the same clock phase and polarity. The SPI module should be disabled (by
clearing the SPIEN bit) when changing the clock phase or polarity. Note that CKPHA should be set to 0 on both the master and slave
SPI when communicating between two Silicon Labs devices.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO/MOSI
Figure 19.5. Master Mode Data/Clock Timing
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO
NSS (4-Wire Mode)
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MOSI
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
Figure 19.6. Slave Mode Data/Clock Timing (CKPHA = 0)
EFM8SB2 Reference Manual
Serial Peripheral Interfaces (SPI0 and SPI1)
silabs.com
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