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Silicon Laboratories EFM8SB2, Reference Manual

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20.3.4  Hardware ACK Multimaster and Multislave Behavior

In some system management bus (SMBus) configurations, the hardware ACK mechanism of the SMBus peripheral can cause incorrect
or undesired behavior. The hardware ACK mechanism is enabled when the EHACK bit in the SMB0ADM register is set to logic 1. The
configurations to which this behavior does not apply are as follows:

1. All SMBus configurations when hardware ACK is disabled.
2. All single-master / single-slave SMBus configurations when hardware ACK is enabled and the MCU is operating as a master or

slave.

3. All multi-master / single-slave SMBus configurations when hardware ACK is enabled and the MCU is operating as a slave.
4. All single-master / multi-slave SMBus configurations when hardware ACK is enabled and the MCU is operating as a master.

This behavior only applies to the following configurations:

1. All multi-slave SMBus configurations when hardware ACK is enabled and the MCU is operating as a slave.
2. All multi-master SMBus configurations when hardware ACK is enabled and the MCU is operating as a master.

Multi-Slave Behavior

The following issues are present when operating as a slave in a multi-slave SMBus configuration:

1. When hardware ACK is enabled and SDA setup and hold times are not extended (EXTHOLD = 0 in the SMB0CF register), the

SMBus hardware will always generate an SMBus interrupt following the ACK/NACK cycle of any slave address transmission on the
bus, whether or not the address matches the conditions of SMB0ADR and SMB0ADM. The expected behavior is that an interrupt is
only generated when the address matches.

2. When hardware ACK is enabled and SDA setup and hold times are extended (EXTHOLD = 1 in the SMB0CF register), the SMBus

hardware will only generate an SMBus interrupt as expected when the slave address transmission on the bus matches the condi-
tions of SMB0ADR and SMB0ADM. However, in this mode, the start bit (STA) will be incorrectly cleared on reception of a slave
address before firmware vectors to the interrupt service routine.

3. When hardware ACK is enabled and the ACK bit in the SMB0CN0 register is set to 1, an unaddressed slave may cause interfer-

ence on the SMBus by driving SDA low during an ACK cycle. The ACK bit of the unaddressed slave may be set to 1 if any device
on the bus generates an ACK.

Once the CPU enters the interrupt service routine, SCL will be asserted low until SI is cleared, causing the clock to be stretched when
the MCU is not being addressed. This may limit the maximum speed of the SMBus if the master supports SCL clock stretching. Incom-
pliant SMBus masters that do not support SCL clock stretching will not recognize that the clock is being stretched. If the CPU issues a
write to SMB0DAT, it will have no effect on the bus. No data collisions will occur. To work around this issue, the SMBus interrupt serv-
ice routine should verify an address when it is received and clear SI as soon as possible if the address does not match to minimize
clock stretching. To prevent clock stretching when not being addressed, enable setup and hold time extensions (EXTHOLD = 1).

Once the hardware has matched an address and entered the interrupt service routine, the firmware will not be able to use the start bit
to distinguish between the reception of an address byte versus the reception of a data byte. However, the hardware will still correctly
acknowledge the address byte (SLA+R/W). During an initial start sequence, to distinguish between the reception of an address byte at
the beginning of a transfer versus the reception of a data byte when setup and hold time extensions are enabled (EXTHOLD = 1), firm-
ware should maintain a status bit to determine whether it is currently inside or outside a transfer. Once hardware detects a matching
slave address and interrupts the MCU, firmware should assume a start condition and set the firmware bit to indicate that it is currently
inside a transfer. A transfer ends any time the STO bit is set or on an error condition (e.g., SCL Low Timeout). During a repeated start
sequence,  to  detect  the  reception  of  an  address  byte  in  the  middle  of  a  transfer  when  setup  and  hold  time  extensions  are  enabled
(EXTHOLD = 1), disable setup and hold time extensions (EXTHOLD = 0) upon entry into a transfer and re-enable setup and hold time
extensions (EXHOLD = 1) at the end of a transfer.

The SMBus master and the addressed slave are prevented from generating a NACK by the unaddressed slave because it is holding
SDA low during the ACK cycle. There is a potential for the SMBus to lock up in this situation. To prevent this, schedule a timer interrupt
to clear the ACK bit at an interval shorter than 7 bit periods when the slave is not being addressed. For example, on a 400 kHz SMBus,
the ACK bit should be cleared every 17.5 μs (or at 1/7 the bus frequency, 57 kHz). As soon as a matching slave address is detected (a
transfer is started), the timer which clears the ACK bit should be stopped and its interrupt flag cleared. The timer should be re-started
once a stop or error condition is detected (the transfer has ended).

Multi-Master Behavior

When operating as a master in a multi-master SMBus configuration, if the SMBus master loses arbitration, it may cause interference on
the SMBus by driving SDA low during the ACK cycle of transfers in which it is not participating. This will occur regardless of the state of
the ACK bit in the SMB0CN0 register. In this case, the SMBus master and slave participating in the transfer are prevented from gener-
ating a NACK by the MCU because it is holding SDA low during the ACK cycle. There is a potential for the SMBus to lock up.

To work around this behavior, firmware should disable hardware ACK (EHACK = 0) when the MCU is operating as a master in a multi-
master SMBus configuration.

EFM8SB2 Reference Manual

System Management Bus / I2C (SMB0)

silabs.com

 | Smart. Connected. Energy-friendly.

Rev. 0.1  |  231

Summary of Contents for EFM8SB2

Page 1: ...out detection 300 nA Ultra fast wake up for digital and analog peripherals 2 μs Integrated low drop out LDO voltage regulator to maintain ultra low active current at all voltages Hand held devices Industrial controls Battery operated consumer electronics Sensor interfaces Security I O Ports Core Memory Clock Management CIP 51 8051 Core 25 MHz Energy Management Internal LDO Regulator Brown Out Dete...

Page 2: ...ision 24 5 MHz Oscillator Debug Programming Hardware Power On Reset PMU Reset C2D C2CK RSTb Wake XTAL2 Low Power 20 MHz Oscillator XTAL3 XTAL4 VREG Digital Power Analog Power Port 0 Drivers Port 1 Drivers Port 2 Drivers P2 n RTC Oscillator CRC External Memory Interface Control Address Data Analog Peripherals SFR Bus Comparators 6 bit IREF IREF0 AMUX 10 bit 300ksps ADC Temp Sensor External VREF Int...

Page 3: ...RTC0 Fail Event Port Match Event Comparator 0 Rising Edge 1 3 I O Digital and analog resources are externally available on the device s multi purpose I O pins Port pins P0 0 P2 6 can be defined as gen eral purpose I O GPIO assigned to one of the internal digital resources through the crossbar or dedicated channels or assigned to an analog function Port pin P2 7 can be used as GPIO Additionally the...

Page 4: ...s routed through the crossbar to port I O when enabled 16 bit time base Programmable clock divisor and clock source selection Up to six independently configurable channels 8 9 10 11 and 16 bit PWM modes edge aligned operation Frequency output mode Capture on rising falling or any edge Compare function for arbitrary waveform generation Software timer internal compare mode Integrated watchdog timer ...

Page 5: ...us serial bus The SPI can operate as a master or slave device in both 3 wire or 4 wire modes and supports multiple masters and slaves on a single SPI bus The slave select NSS signal can be configured as an input to select the SPI in slave mode or to disable master mode operation in a multi master environment avoiding contention on the SPI bus when more than one master attempts simultaneous data tr...

Page 6: ...automatically CRC the flash contents of the device The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols The CRC module includes the following features Support for CCITT 16 polynomial 0x1021 Support for CRC 32 polynomial 0x04C11DB7 Byte level bit reversal Automatic CRC of flash contents on one or more 1024 byte blocks Initial seed se...

Page 7: ...pare interrupts supported Flexible output data formatting Includes an internal 1 65 V fast settling reference and support for external reference Integrated temperature sensor Low Current Comparators CMP0 CMP1 Analog comparators are used to compare the voltage of two analog inputs with a digital output indicating which input voltage is higher External input connections to device I O pins and intern...

Page 8: ... the program counter PC is reset and the system clock defaults to an internal oscillator The Watchdog Timer is enabled and program execution begins at location 0x0000 Reset sources on the device include the following Power on reset External reset pin Comparator reset Software triggered reset Supply monitor reset monitors VDD supply Watchdog timer reset Missing clock detector reset Flash error rese...

Page 9: ...ccessed using MOVX instructions Total RAM varies based on the specific device The device memory map has more details about the specific amount of RAM available in each area for the different device variants Internal RAM There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF The lower 128 bytes of data memo ry are used for general purpose registers and scratch ...

Page 10: ...r s stack can be located anywhere in the 256 byte data memory The stack area is designated using the Stack Pointer SP SFR The SP will point to the last location used The next value pushed on the stack is placed at SP 1 and then SP is incremen ted A reset initializes the stack pointer to location 0x07 Therefore the first value pushed on the stack is placed at location 0x08 which is also the first r...

Page 11: ... 63 x 1024 Byte pages 0xF800 0xFBFE 0xFBFF Lock Byte Reserved 0xFFFF 0x0000 Scratchpad 1024 Bytes 0x0000 0x03FF Figure 2 1 Flash Memory Map 64 KB Devices EFM8SB2 Reference Manual Memory Organization silabs com Smart Connected Energy friendly Rev 0 1 10 ...

Page 12: ...024 Byte pages 0x7C00 0x7FFE 0x7FFF Lock Byte Reserved 0xFFFF 0x0000 Scratchpad 1024 Bytes 0x0000 0x03FF Figure 2 2 Flash Memory Map 32 KB Devices EFM8SB2 Reference Manual Memory Organization silabs com Smart Connected Energy friendly Rev 0 1 11 ...

Page 13: ... 128 Bytes RAM Direct or Indirect Access 0x00 0x1F General Purpose Register Banks Bit Addressable 0x20 0x2F 0x30 0x7F Upper 128 Bytes RAM Indirect Access Special Function Registers Direct Access 0x80 0xFF On Chip RAM Accessed with MOV Instructions as Indicated Figure 2 4 Direct Indirect RAM Memory EFM8SB2 Reference Manual Memory Organization silabs com Smart Connected Energy friendly Rev 0 1 12 ...

Page 14: ...nstructions XRAM 4096 Bytes 0x0000 0x0FFF 0x1000 Shadow XRAM Duplicates 0x0000 0x0FFF On 4096 B boundaries 0xFFFF Figure 2 5 XRAM Memory EFM8SB2 Reference Manual Memory Organization silabs com Smart Connected Energy friendly Rev 0 1 13 ...

Page 15: ... The SFR memory space has 256 pages In this way each memory location from 0x80 to 0xFF can access up to 256 SFRs The EFM8SB2 devices utilize multiple SFR pages All of the common 8051 SFRs are available on all pages Certain SFRs are only available on a subset of pages SFR pages are selected using the SFRPAGE register The procedure for reading and writing an SFR is as follows 1 Select the appropriat...

Page 16: ...0xCB TMR2RLH 0x8C TH0 0xCC TMR2L 0x8D TH1 0xCD TMR2H 0x8E CKCON0 0xCE PCA0CPM5 0x8F PSCTL 0xCF P1MAT 0x90 P1 0xD0 PSW 0x91 TMR3CN0 CRC0DAT 0xD1 REF0CN 0x92 TMR3RLL CRC0CN0 0xD2 PCA0CPL5 0x93 TMR3RLH CRC0IN 0xD3 PCA0CPH5 0x94 TMR3L 0xD4 P0SKIP 0x95 TMR3H CRC0FLIP 0xD5 P1SKIP 0x96 CRC0AUTO 0xD6 P2SKIP 0x97 CRC0CNT 0xD7 P0MAT 0x98 SCON0 0xD8 PCA0CN0 0x99 SBUF0 0xD9 PCA0MD 0x9A CMP1CN0 0xDA PCA0CPM0 0...

Page 17: ... RSTSRC 0xB0 SPI1CN0 0xF0 B 0xB1 XOSC0CN 0xF1 P0MDIN 0xB2 HFO0CN 0xF2 P1MDIN 0xB3 HFO0CAL 0xF3 P2MDIN 0xB4 0xF4 SMB0ADR 0xB5 PMU0CF 0xF5 SMB0ADM 0xB6 FLSCL 0xF6 EIP1 0xB7 FLKEY 0xF7 EIP2 0xB8 IP 0xF8 SPI0CN0 0xB9 IREF0CN0 0xF9 PCA0L 0xBA ADC0AC ADC0PWR 0xFA PCA0H 0xBB ADC0MX 0xFB PCA0CPL0 0xBC ADC0CF 0xFC PCA0CPH0 0xBD ADC0L ADC0TK 0xFD PCA0CPL4 0xBE ADC0H 0xFE PCA0CPH4 0xBF P1MASK 0xFF VDM0CN Tab...

Page 18: ...CMP1CN0 0x9A 0x00 Comparator 1 Control 0 CMP1MD 0x9C 0x00 Comparator 1 Mode CMP1MX 0x9E 0x00 Comparator 1 Multiplexer Selection CRC0AUTO 0x96 0x0F CRC0 Automatic Control CRC0CN0 0x92 0x0F CRC0 Control 0 CRC0CNT 0x97 0x0F CRC0 Automatic Flash Sector Count CRC0DAT 0x91 0x0F CRC0 Data Output CRC0FLIP 0x95 0x0F CRC0 Bit Flip CRC0IN 0x93 0x0F CRC0 Data Input DPH 0x83 ALL Data Pointer High DPL 0x82 ALL ...

Page 19: ...Skip P2 0xA0 ALL Port 2 Pin Latch P2DRV 0xA6 0x0F Port 2 Drive Strength P2MDIN 0xF3 0x00 Port 2 Input Mode P2MDOUT 0xA6 0x00 Port 2 Output Mode P2SKIP 0xD6 0x00 Port 2 Skip PCA0CN0 0xD8 0x00 PCA Control 0 PCA0CPH0 0xFC 0x00 PCA Channel 0 Capture Module High Byte PCA0CPH1 0xEA 0x00 PCA Channel 1 Capture Module High Byte PCA0CPH2 0xEC 0x00 PCA Channel 2 Capture Module High Byte PCA0CPH3 0xEE 0x00 PC...

Page 20: ...xD0 ALL Program Status Word REF0CN 0xD1 0x00 Voltage Reference Control REG0CN 0xC9 0x00 Voltage Regulator Control RSTSRC 0xEF 0x00 Reset Source RTC0ADR 0xAC 0x00 RTC Address RTC0DAT 0xAD 0x00 RTC Data RTC0KEY 0xAE 0x00 RTC Lock and Key SBUF0 0x99 0x00 UART0 Serial Port Data Buffer SCON0 0x98 0x00 UART0 Serial Port Control SFRPAGE 0xA7 ALL SFR Page SMB0ADM 0xF5 0x00 SMBus 0 Slave Address Mask SMB0A...

Page 21: ...3 0x00 Timer 3 Reload High Byte TMR3RLL 0x92 0x00 Timer 3 Reload Low Byte TOFFH 0x86 0x0F Temperature Sensor Offset High TOFFL 0x85 0x0F Temperature Sensor Offset Low VDM0CN 0xFF 0x00 VDD Supply Monitor Control XBR0 0xE1 0x00 Port I O Crossbar 0 XBR1 0xE2 0x00 Port I O Crossbar 1 XBR2 0xE3 0x00 Port I O Crossbar 2 XOSC0CN 0xB1 0x00 External Oscillator Control 3 3 SFR Access Control Registers 3 3 1...

Page 22: ...ce or from firmware by overloading the MOVX instruction Any individual byte in flash memory must only be written once between page erase operations Security Page 1024 Bytes 63 KB Flash 63 x 1024 Byte pages 0xF800 0xFBFE 0xFBFF Lock Byte Reserved 0xFFFF 0x0000 Scratchpad 1024 Bytes 0x0000 0x03FF Figure 4 1 Flash Memory Map 64 KB Devices EFM8SB2 Reference Manual Flash Memory silabs com Smart Connect...

Page 23: ...x 1024 Byte pages 0x7C00 0x7FFE 0x7FFF Lock Byte Reserved 0xFFFF 0x0000 Scratchpad 1024 Bytes 0x0000 0x03FF Figure 4 2 Flash Memory Map 32 KB Devices EFM8SB2 Reference Manual Flash Memory silabs com Smart Connected Energy friendly Rev 0 1 22 ...

Page 24: ...ry Map 16 KB Devices 4 2 Features The flash memory has the following features Up to 64 KB organized in 1024 byte sectors In system programmable from user firmware Security lock to prevent unwanted read write erase access 1024 bytes of non volatile data storage in the Scratchpad EFM8SB2 Reference Manual Flash Memory silabs com Smart Connected Energy friendly Rev 0 1 23 ...

Page 25: ...Lock Byte is unlocked when no other flash pages are locked all bits of the Lock Byte are 1 and locked when any other flash pages are locked any bit of the Lock Byte is 0 Table 4 1 Security Byte Decoding Security Lock Byte 111111101b 1s Complement 00000010b Flash Pages Locked 3 First two flash pages Lock Byte Page The level of flash security depends on the flash access method The three flash access...

Page 26: ...n can be performed 4 3 2 2 Flash Page Erase Procedure The flash memory is erased one page at a time by firmware using the MOVX write instruction with the address targeted to any byte within the page Before erasing a page of flash memory flash write and erase operations must be enabled by setting the PSWE and PSEE bits in the PSCTL register to logic 1 this directs the MOVX writes to target flash me...

Page 27: ...ther condition is not met As an added precaution if the supply monitor is ever disabled explicitly enable the supply monitor and enable the supply monitor as a reset source inside the functions that write and erase flash memory The supply monitor enable instructions should be placed just after the instruction to set PSWE to a 1 but before the flash write or erase operation instruction Make certain...

Page 28: ... 0 Reduce Toggling Lines in Loops Flash read current depends on the number of address lines that toggle between sequential flash read operations In most cases the difference in power is relatively small on the order of 5 The flash memory is organized in rows of 128 bytes A substantial current increase can be detected when the read address jumps from one row in the flash memory to another Consider ...

Page 29: ...Erase Enable Setting this bit in combination with PSWE allows an entire page of flash program memory to be erased If this bit is logic 1 and flash writes are enabled PSWE is logic 1 a write to flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction The value of the data byte written does not matter Value Name Description 0 ERA...

Page 30: ...11 Flash writes erases are disabled until the next reset 4 4 3 FLSCL Flash Scale Bit 7 6 5 4 3 2 1 0 Name Reserved BYPASS Reserved Access R RW R Reset 0 0 0x00 SFR Page 0x0 SFR Address 0xB6 Bit Name Reset Access Description 7 Reserved Must write reset value 6 BYPASS 0 RW Flash Read Timing One Shot Bypass Value Name Description 0 ONE_SHOT The one shot determines the flash read time This setting sho...

Page 31: ...mal operation The bytes in memory will be automatically reini tialized with the UID value after any device reset Firmware using this area of memory should always initialize the memory to a known value as any previous data stored at these locations will be overwritten and not retained through a reset Table 5 1 UID Location in Memory Device XRAM Addresses EFM8SB20F64G EFM8SB20F32G MSB 0x0FFF 0x0FFE ...

Page 32: ... to logic 1 If interrupts are enabled for the flag an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt pending flag Refer to the data sheet section associated with a particular on chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt pending flag s 6 2 1 Interrupt Priorit...

Page 33: ...RM ADC0 Window Compare 0x004B 9 EIE1_EWADC0 ADC0CN0_ADWINT ADC0 End of Conversion 0x0053 10 EIE1_EADC0 ADC0CN0_ADINT PCA0 0x005B 11 EIE1_EPCA0 PCA0CPM0_ECCF PCA0CPM1_ECCF PCA0CPM2_ECCF PCA0CPM3_ECCF PCA0CPM4_ECCF PCA0CPM5_ECCF PCA0CN0_CCF0 PCA0CN0_CCF1 PCA0CN0_CCF2 PCA0CN0_CCF3 PCA0CN0_CCF4 PCA0CN0_CCF5 PCA0CN0_CF Comparator 0 0x0063 12 EIE1_ECP0 CMP0MD_CPFIE CMP0MD_CPRIE CMP0CN0_CPFIF CMP0CN0_CPR...

Page 34: ...riority Primary Enable Auxiliary Enable s Pending Flag s SPI1 0x0093 18 EIE2_ESPI1 SPI1CN0_MODF SPI1CN0_RXOVRN SPI1CN0_SPIF SPI1CN0_WCOL EFM8SB2 Reference Manual Interrupts silabs com Smart Connected Energy friendly Rev 0 1 33 ...

Page 35: ...e Description 0 DISABLED Disable all SPI0 interrupts 1 ENABLED Enable interrupt requests generated by SPI0 5 ET2 0 RW Timer 2 Interrupt Enable This bit sets the masking of the Timer 2 interrupt Value Name Description 0 DISABLED Disable Timer 2 interrupt 1 ENABLED Enable interrupt requests generated by the TF2L or TF2H flags 4 ES0 0 RW UART0 Interrupt Enable This bit sets the masking of the UART0 i...

Page 36: ...le This bit sets the masking of the Timer 0 interrupt Value Name Description 0 DISABLED Disable all Timer 0 interrupt 1 ENABLED Enable interrupt requests generated by the TF0 flag 0 EX0 0 RW External Interrupt 0 Enable This bit sets the masking of External Interrupt 0 Value Name Description 0 DISABLED Disable external interrupt 0 1 ENABLED Enable interrupt requests generated by the INT0 input EFM8...

Page 37: ...set to high priority level 4 PS0 0 RW UART0 Interrupt Priority Control This bit sets the priority of the UART0 interrupt Value Name Description 0 LOW UART0 interrupt set to low priority level 1 HIGH UART0 interrupt set to high priority level 3 PT1 0 RW Timer 1 Interrupt Priority Control This bit sets the priority of the Timer 1 interrupt Value Name Description 0 LOW Timer 1 interrupt set to low pr...

Page 38: ...iority level 0 PX0 0 RW External Interrupt 0 Priority Control This bit sets the priority of the External Interrupt 0 interrupt Value Name Description 0 LOW External Interrupt 0 set to low priority level 1 HIGH External Interrupt 0 set to high priority level EFM8SB2 Reference Manual Interrupts silabs com Smart Connected Energy friendly Rev 0 1 37 ...

Page 39: ...CP0 Interrupt Enable This bit sets the masking of the CP0 interrupt Value Name Description 0 DISABLED Disable CP0 interrupts 1 ENABLED Enable interrupt requests generated by the comparator 0 CPRIF or CPFIF flags 4 EPCA0 0 RW Programmable Counter Array PCA0 Interrupt Enable This bit sets the masking of the PCA0 interrupts Value Name Description 0 DISABLED Disable all PCA0 interrupts 1 ENABLED Enabl...

Page 40: ...asking of the RTC Alarm interrupt Value Name Description 0 DISABLED Disable RTC Alarm interrupts 1 ENABLED Enable interrupt requests generated by a RTC Alarm 0 ESMB0 0 RW SMBus SMB0 Interrupt Enable This bit sets the masking of the SMB0 interrupt Value Name Description 0 DISABLED Disable all SMB0 interrupts 1 ENABLED Enable interrupt requests generated by SMB0 EFM8SB2 Reference Manual Interrupts s...

Page 41: ...ity Control This bit sets the priority of the CP0 interrupt Value Name Description 0 LOW CP0 interrupt set to low priority level 1 HIGH CP0 interrupt set to high priority level 4 PPCA0 0 RW Programmable Counter Array PCA0 Interrupt Priority Control This bit sets the priority of the PCA0 interrupt Value Name Description 0 LOW PCA0 interrupt set to low priority level 1 HIGH PCA0 interrupt set to hig...

Page 42: ...C Alarm interrupt Value Name Description 0 LOW RTC Alarm interrupt set to low priority level 1 HIGH RTC Alarm interrupt set to high priority level 0 PSMB0 0 RW SMBus SMB0 Interrupt Priority Control This bit sets the priority of the SMB0 interrupt Value Name Description 0 LOW SMB0 interrupt set to low priority level 1 HIGH SMB0 interrupt set to high priority level EFM8SB2 Reference Manual Interrupt...

Page 43: ...terrupt Value Name Description 0 DISABLED Disable RTC Oscillator Fail interrupts 1 ENABLED Enable interrupt requests generated by the RTC Oscillator Fail event 1 EMAT 0 RW Port Match Interrupts Enable This bit sets the masking of the Port Match event interrupt Value Name Description 0 DISABLED Disable all Port Match interrupts 1 ENABLED Enable interrupt requests generated by a Port Match 0 EWARN 0...

Page 44: ...rrupt Value Name Description 0 LOW RTC Oscillator Fail interrupt set to low priority level 1 HIGH RTC Oscillator Fail interrupt set to high priority level 1 PMAT 0 RW Port Match Interrupt Priority Control This bit sets the priority of the Port Match Event interrupt Value Name Description 0 LOW Port Match interrupt set to low priority level 1 HIGH Port Match interrupt set to high priority level 0 P...

Page 45: ...ce Port I O Pins Figure 7 1 Power System Block Diagram Table 7 1 Power Modes Power Mode Details Mode Entry Wake Up Sources Normal Core and all peripherals clocked and fully operational Idle Core halted All peripherals clocked and fully operational Code resumes execution on wake event Set IDLE bit in PCON0 Any interrupt Suspend Core and digital peripherals halted Internal oscillators disabled Code ...

Page 46: ...bit PCON0 PCON0 followed by a 3 cycle dummy instruction in assembly ORL PCON0 01h set IDLE bit MOV PCON0 PCON0 followed by a 3 cycle dummy instruction If enabled the Watchdog Timer WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode This fea ture protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON0 register...

Page 47: ...synchronizes with the core Suspend mode is terminated by any enabled wake or reset source When suspend mode is terminated the device will continue execu tion on the instruction following the one that set the SUSPEND bit If the wake event was configured to generate an interrupt the inter rupt will be serviced upon waking the device If suspend mode is terminated by an internal or external reset the ...

Page 48: ...olatile state information is preserved allowing the device to resume code execution upon waking up from sleep mode The following wake up sources can be configured to wake the device from sleep mode RTC oscillator fail RTC alarm Port match event Comparator 0 rising edge The comparator requires a supply voltage of at least 1 8 V to operate properly In addition any falling edge on RSTb due to a pin r...

Page 49: ...F0 STOP IDLE Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0x87 Bit Name Reset Access Description 7 GF5 0 RW General Purpose Flag 5 This flag is a general purpose flag for use under firmware control 6 GF4 0 RW General Purpose Flag 4 This flag is a general purpose flag for use under firmware control 5 GF3 0 RW General Purpose Flag 3 This flag is a general purpose fla...

Page 50: ...le wake up on an RTC Alarm 1 PMATWK Varies RW Port Match Wake up Source Enable and Flag Read Hardware sets this bit to 1 if Port Match event occured Write Write this bit to 1 to enable wake up on a Port Match event 0 CPT0WK Varies RW Comparator0 Wake up Source Enable and Flag Read Hardware sets this bit to 1 if a Comparator 0 rising edge caused the last wake up Write Write this bit to 1 to enable ...

Page 51: ...Bias When set to 1 the bias used by the precision High Frequency Oscillator is forced on If the precision oscillator is not being used this bit may be cleared to 0 to reduce supply current in all non Sleep power modes If disabled then re enabled the precision oscillator bias requires 4 us of settling time 3 0 Reserved Must write reset value EFM8SB2 Reference Manual Power Management and Internal Re...

Page 52: ... as the system clock while CLKDIV controls the programmable divider When an internal oscillator source is selected as the SYSCLK the external oscillator may still clock certain peripherals In these cases the external oscillator source is synchronized to the SYSCLK source The system clock may be switched on the fly between any of the oscillator sources so long as the selected clock source is enable...

Page 53: ...er an external 32 kHz crystal or an internal 16 4 kHz 20 low frequency oscillator LFOSC0 No loading capacitors are required for the crystal and it can be connected directly to the XTAL3 and XTAL4 pins EFM8SB2 Reference Manual Clocking and Oscillators silabs com Smart Connected Energy friendly Rev 0 1 52 ...

Page 54: ... is 2 5 pF per pin If CA and CB are the same C then the equation becomes the following CL C 2 CS Figure 8 3 External Oscillator Load Capacitance with Equal Capacitors For example a tuning fork crystal of 25 MHz has a recommended load capacitance of 12 5 pF With a stray capacitance of 3 pF per pin 6 pF total the 13 pF capacitors yield an equivalent capacitance of 12 5 pF across the crystal 15 pF 15...

Page 55: ...system clock has stabilized Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior The recommended procedure for starting the crystal is as follows 1 Configure XTAL1 and XTAL2 for analog I O and disable the digital output drivers 2 Disable the XTAL1 and XTAL2 digital output drivers by writing 1 s to the appropriate bits in the port la...

Page 56: ...he pull up resistor value in kΩ f 1 23 103 R C Figure 8 6 RC Mode Oscillator Frequency For example if the frequency desired is 100 kHz let R 246 kΩ and C 50 pF f 1 23 103 R C 1 23 103 246 50 100 kHz Figure 8 7 RC Mode Oscillator Example Referencing the recommended XFCN setting for 100 kHz is 010 When the RC oscillator is first enabled the external oscillator valid detector allows firmware to deter...

Page 57: ...n frequency and the required XFCN field value determined by the following equation where f is the frequency in MHz C is the capacitor value on XTAL2 in pF and VDD is the power supply voltage in Volts f KF C VDD Figure 8 9 C Mode Oscillator Frequency For example assume VDD 3 0 V and f 150 kHz Since a frequency of roughly 150 kHz is desired select the K Factor from as KF 22 f KF C VDD 0 150 MHz 22 C...

Page 58: ...l CMOS An external CMOS clock source is also supported as a core clock source The XTAL2 EXTCLK pin on the device serves as the external clock input when running in this mode When not selected as the SYSCLK source the EXTCLK input is always re synchronized to SYSCLK XTAL1 is not used in external CMOS clock mode Note When selecting the EXTCLK pin as a clock input source the pin should be skipped in ...

Page 59: ...CLK is equal to selected clock source divided by 4 0x3 SYSCLK_DIV_8 SYSCLK is equal to selected clock source divided by 8 0x4 SYSCLK_DIV_16 SYSCLK is equal to selected clock source divided by 16 0x5 SYSCLK_DIV_32 SYSCLK is equal to selected clock source divided by 32 0x6 SYSCLK_DIV_64 SYSCLK is equal to selected clock source divided by 64 0x7 SYSCLK_DIV_128 SYSCLK is equal to selected clock source...

Page 60: ...5 MHz 8 4 3 HFO0CN High Frequency Oscillator Control Bit 7 6 5 4 3 2 1 0 Name IOSCEN IFRDY Reserved Access RW R RW Reset 0 0 0x0F SFR Page 0x0 SFR Address 0xB2 Bit Name Reset Access Description 7 IOSCEN 0 RW High Frequency Oscillator Enable Value Name Description 0 DISABLED High Frequency Oscillator disabled 1 ENABLED High Frequency Oscillator enabled 6 IFRDY 0 R Internal Oscillator Frequency Read...

Page 61: ...ernal Oscillator is running and stable 6 4 XOSCMD 0x0 RW External Oscillator Mode Value Name Description 0x0 DISABLED External Oscillator circuit disabled 0x2 CMOS External CMOS Clock Mode 0x3 CMOS_DIV_2 External CMOS Clock Mode with divide by 2 stage 0x4 RC RC Oscillator Mode 0x5 C Capacitor Oscillator Mode 0x6 CRYSTAL Crystal Oscillator Mode 0x7 CRYSTAL_DIV_2 Crystal Oscillator Mode with divide ...

Page 62: ...face consists of three registers RTC0KEY RTC0ADR and RTC0DAT These interface registers are located on the SFR map and provide access to the RTC internal registers The RTC internal registers can only be accessed indirectly through the RTC interface The RTC interface is protected with a lock and key function The RTC lock and key register RTC0KEY must be written with the correct key codes in sequence...

Page 63: ...a from the selected register to RTC0DAT 4 Poll BUSY until it returns 0 or follow the recommend instruction timing 5 Read the data from RTC0DAT Note The RTC0ADR and RTC0DAT registers will retain their state upon a device reset Short Strobe Feature Reads and writes to indirect RTC registers normally take 7 system clock cycles To minimize the indirect register access time the short strobe feature dec...

Page 64: ...XCF 5 Enable power to the RTC oscillator circuit RTC0EN 1 6 Wait 20 ms 7 Poll the RTC clock valid flag CLKVLD until the crystal oscillator stabilizes 8 Poll the RTC load capacitance ready flag LOADRDY until the load capacitance reaches its programmed value 9 Enable automatic gain control AGCEN and disable bias doubling BIASX2 for maximum power savings 10 Enable the RTC missing clock detector 11 Wa...

Page 65: ...nal programmed value is reached The final programmed loading capacitor value is specified using the LOADCAP field in the RTC0XCF register The LOADCAP setting specifies the amount of on chip load capacitance and does not include any stray PCB capacitance Once the final programmed loading capacitor value is reached hardware will set the LOADRDY flag to 1 When using the RTC oscillator in self oscilla...

Page 66: ...scillation As the duty cycle approaches 60 oscillation becomes less reliable and the risk of clock failure increases Increasing the bias current by disabling AGC will always improve oscillation robustness and will reduce the output clock s duty cycle This test should be performed at the worst case system conditions as results at very low temperatures or high supply voltage will vary from results t...

Page 67: ... or read using the CAPTUREn internal registers Note that the timer does not need to be stopped be fore reading or setting its value The following steps can be used to set the timer value 1 Write the desired 32 bit set value to the CAPTUREn registers 2 Write 1 to RTC0SET This will transfer the contents of the CAPTUREn registers to the RTC timer 3 The operation is complete when RTC0SET is cleared to...

Page 68: ...ach alarm The alarm interval is managed by hardware and stored in the ALRMn registers Software only needs to set the alarm interval once during device initialization After each alarm software should keep a count of the number of alarms that have occurred in order to keep track of time This mode is ideal for applications that require minimal software intervention and or have a fixed alarm interval ...

Page 69: ...C indirect read operation is initiated when firmware reads the RTC0DAT register 5 Reserved Must write reset value 4 SHORT 0 RW Short Strobe Enable Enables disables the Short Strobe feature Value Name Description 0 DISABLED Disable short strobe 1 ENABLED Enable short strobe 3 0 ADDR 0x0 RW RTC Indirect Register Address Sets the currently selected RTC internal register The ADDR bits increment after ...

Page 70: ...dware when a missing RTC detector timeout occurs Must be cleared by firmware The value of this bit is not defined when the RTC oscillator is disabled 4 RTC0TR 0 RW RTC Timer Run Control Controls if the RTC timer is running or stopped holds current value Value Name Description 0 STOP RTC timer is stopped 1 RUN RTC timer is running 3 RTC0AEN 0 RW RTC Alarm Enable Enables disables the RTC alarm funct...

Page 71: ...operation is complete 0 RTC0CAP 0 RW RTC Timer Capture Writing 1 initiates a RTC timer capture operation This bit is cleared to 0 by hardware to indicate that the timer capture oper ation is complete The ALRM flag will remain asserted for a maximum of one RTC cycle This register is accessed indirectly using the RTC0ADR and RTC0DAT registers EFM8SB2 Reference Manual Real Time Clock RTC0 silabs com ...

Page 72: ...SX2 0 RW RTC Oscillator Bias Double Enable Enables disables the Bias Double feature Value Name Description 0 DISABLED Disable the Bias Double feature 1 ENABLED Enable the Bias Double feature 4 CLKVLD 0 R RTC Oscillator Crystal Valid Indicator Indicates if oscillation amplitude is sufficient for maintaining oscillation Value Name Description 0 NOT_SET Oscillation has not started or oscillation ampl...

Page 73: ...tepping 1 SET Load capacitance has reached it programmed value 5 4 Reserved Must write reset value 3 0 LOADCAP Varies RW Load Capacitance Programmed Value Holds the desired load capacitance value This register is accessed indirectly using the RTC0ADR and RTC0DAT registers 9 4 7 CAPTURE0 RTC Timer Capture 0 Bit 7 6 5 4 3 2 1 0 Name CAPTURE0 Access RW Reset 0x00 Indirect Address 0x00 Bit Name Reset ...

Page 74: ...0 RW RTC Timer Capture 2 The CAPTURE3 CAPTURE0 registers are used to read or set the 32 bit RTC timer Data is transferred to or from the RTC timer when the RTC0SET or RTC0CAP bits are set This register is accessed indirectly using the RTC0ADR and RTC0DAT registers 9 4 10 CAPTURE3 RTC Timer Capture 3 Bit 7 6 5 4 3 2 1 0 Name CAPTURE3 Access RW Reset 0x00 Indirect Address 0x03 Bit Name Reset Access ...

Page 75: ... 0x00 RW RTC Alarm Programmed Value 1 The ALARM3 ALARM0 registers are used to set an alarm event for the RTC timer The RTC alarm should be disabled RTC0AEN 0 when updating these registers This register is accessed indirectly using the RTC0ADR and RTC0DAT registers 9 4 13 ALARM2 RTC Alarm Programmed Value 2 Bit 7 6 5 4 3 2 1 0 Name ALARM2 Access RW Reset 0x00 Indirect Address 0x0A Bit Name Reset Ac...

Page 76: ...ectly using the RTC0ADR and RTC0DAT registers 9 4 15 RTC0PIN RTC Pin Configuration Bit 7 6 5 4 3 2 1 0 Name RTCPIN Access W Reset 0x67 Indirect Address 0x07 Bit Name Reset Access Description 7 0 RTCPIN 0x67 W RTC Pin Configuration Writing 0xE7 to this field forces XTAL3 and XTAL4 to be internally shorted for use with self oscillate mode Writing 0x67 returns XTAL3 and XTAL4 to their normal configur...

Page 77: ...Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to an internal oscillator The Watchdog Timer is enabled and program execution begins at location 0x0000 Reset Sources RSTb Supply Monitor or Power up Mi...

Page 78: ...ve ly lost even though the data on the stack is not altered The port I O latches are reset to 0xFF all logic ones in open drain mode Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state Note During a power on event there may be a short delay before the POR circuitry fires and the RSTb pin is dri...

Page 79: ... Additionally the power supply must reach VRST before the POR circuit releases the device from reset On exit from a power on reset the PORSF flag is set by hardware to logic 1 When PORSF is set all of the other reset flags in the RSTSRC register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same location 0x0000 software can read the...

Page 80: ...ot enabled any erase or write performed on flash memory will be ignor ed t volts Supply Voltage Reset Threshold VRST Supply Monitor Reset RSTb Figure 10 3 Reset Sources 10 3 4 External Reset The external RSTb pin provides a means for external circuitry to force the device into a reset state Asserting an active low signal on the RSTb pin generates a reset an external pullup and or decoupling of the...

Page 81: ... reserved area A flash read write or erase attempt is restricted due to a flash security setting The FERROR bit is set following a flash error reset The state of the RSTb pin is unaffected by this reset 10 3 9 Software Reset Software may force a reset by writing a 1 to the SWRSF bit The SWRSF bit will read 1 following a software forced reset The state of the RSTb pin is unaffected by this reset 10...

Page 82: ...g timer overflow caused the last reset 2 MCDRSF Varies RW Missing Clock Detector Enable and Flag Read This bit reads 1 if a missing clock detector timeout caused the last reset Write Writing a 1 to this bit enables the missing clock detector The MCD triggers a reset if a missing clock condition is detected 1 PORSF Varies RW Power On Supply Monitor Reset Flag and Supply Monitor Reset Enable Read Th...

Page 83: ...r 1 ENABLED Enable the VDD supply monitor 6 VDDSTAT 0 R V subscript DD subscript Supply Status This bit indicates the current power supply status Value Name Description 0 VDD_BELOW_VRST VDD is at or below the VRST threshold 1 VDD_ABOVE_VRST VDD is above the VRST threshold 5 VDDOK 0 R V subscript DD subscript Supply Status Early Warning This bit indicates the current VDD power supply status Value N...

Page 84: ...n or control system solution DATA BUS TMP1 TMP2 PRGM ADDRESS REG PC INCREMENTER ALU PSW DATA BUS DATA BUS MEMORY INTERFACE MEM_ADDRESS D8 PIPELINE BUFFER DATA POINTER INTERRUPT INTERFACE SYSTEM_IRQs EMULATION_IRQ MEM_CONTROL CONTROL LOGIC A16 PROGRAM COUNTER PC STOP CLOCK RESET IDLE POWER CONTROL REGISTER DATA BUS SFR BUS INTERFACE SFR_ADDRESS SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA D8 D8 B REGIS...

Page 85: ...Power management modes On chip debug logic Program and data memory security 11 3 Functional Description 11 3 1 Programming and Debugging Support In system programming of the flash program memory and communication with on chip debug support logic is accomplished via the Sili con Labs 2 Wire development interface C2 The on chip debug support logic facilitates full speed in circuit debugging allowing...

Page 86: ...emonic number of bytes and number of clock cycles for each instruction Table 11 2 CIP 51 Instruction Set Summary Mnemonic Description Bytes Clock Cycles Arithmetic Operations ADD A Rn Add register to A 1 1 ADD A direct Add direct byte to A 2 2 ADD A Ri Add indirect RAM to A 1 2 ADD A data Add immediate to A 2 2 ADDC A Rn Add register to A with carry 1 1 ADDC A direct Add direct byte to A with carr...

Page 87: ... to direct byte 3 3 CLR A Clear A 1 1 CPL A Complement A 1 1 RL A Rotate A left 1 1 RLC A Rotate A left through Carry 1 1 RR A Rotate A right 1 1 RRC A Rotate A right through Carry 1 1 SWAP A Swap nibbles of A 1 1 Data Transfer MOV A Rn Move Register to A 1 1 MOV A direct Move direct byte to A 2 2 MOV A Ri Move indirect RAM to A 1 2 MOV A data Move immediate to A 2 2 MOV Rn A Move A to Register 1 ...

Page 88: ...ble of indirect RAM with A 1 2 Boolean Manipulation CLR C Clear Carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set Carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement Carry 1 1 CPL bit Complement direct bit 2 2 ANL C bit AND direct bit to Carry 2 2 ANL C bit AND complement of direct bit to Carry 2 2 ORL C bit OR direct bit to carry 2 2 ORL C bit OR complement of direct bit to Carry 2 2 MOV C bit...

Page 89: ...first byte of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s address This could be a direct access Data RAM location 0x00 0x7F or an SFR 0x80 0xFF data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2 KB page of p...

Page 90: ...ddress 0x81 Bit Name Reset Access Description 7 0 SP 0x07 RW Stack Pointer The Stack Pointer holds the location of the top of the stack The stack pointer is incremented before every PUSH operation The SP register defaults to 0x07 after reset 11 4 4 ACC Accumulator Bit 7 6 5 4 3 2 1 0 Name ACC Access RW Reset 0x00 SFR Page ALL SFR Address 0xE0 bit addressable Bit Name Reset Access Description 7 0 A...

Page 91: ...LL SFR Address 0xF0 bit addressable Bit Name Reset Access Description 7 0 B 0x00 RW B Register This register serves as a second accumulator for certain arithmetic operations EFM8SB2 Reference Manual CIP 51 Microcontroller Core silabs com Smart Connected Energy friendly Rev 0 1 90 ...

Page 92: ...Select These bits select which register bank is used during register accesses Value Name Description 0x0 BANK0 Bank 0 Addresses 0x00 0x07 0x1 BANK1 Bank 1 Addresses 0x08 0x0F 0x2 BANK2 Bank 2 Addresses 0x10 0x17 0x3 BANK3 Bank 3 Addresses 0x18 0x1F 2 OV 0 RW Overflow Flag This bit is set to 1 under the following circumstances 1 An ADD ADDC or SUBB instruction causes a sign change overflow 2 A MUL ...

Page 93: ...ort Match P0 P1 P2 P0 P1 P2 ADC0 In P0 P1 P2 P0 P1 P2 P0 P1 P0 Priority Crossbar Decoder P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 7 P1 0 P0 0 VREF P0 1 AGND P0 2 XTAL1 P0 3 XTAL2 P0 4 P0 6 CNVSTR P0 7 IREF0 P0 5 Port Control and Config P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 7 P2 0 Figure 12 1 Port I O Block Diagram 12 2 Features Up to 24 multi functions I O pins supporting digital and analog functions Flexible ...

Page 94: ...r open drain WEAKPUD Weak Pull Up Disable Figure 12 2 Port I O Cell Block Diagram Configuring Port Pins For Analog Modes Any pins to be used for analog functions should be configured for analog mode When a pin is configured for analog I O its weak pull up digital driver and digital receiver are disabled This saves power by eliminating crowbar current and reduces noise on the analog input Pins conf...

Page 95: ...xactly as digital inputs The pin may be driven low by an assigned peripheral or by writing 0 to the associated bit in the Pn register if the signal is a GPIO To configure a pin as a digital push pull output 1 Set the bit associated with the pin in the PnMDIN register to 1 This selects digital mode for the pin 2 Set the bit associated with the pin in the PnMDOUT register to 1 This configures the pi...

Page 96: ...t pin available for assignment by the crossbar This includes P0 0 P2 6 pins which have their PnSKIP bit set to 0 The crossbar will always assign UART0 pins to P0 4 and P0 5 and SPI1 pins to P1 0 P1 3 XBR0 XBR1 XBR2 External Interrupt 0 External Interrupt 1 P0 0 P0 7 IT01CF Conversion Start CNVSTR P0 6 ADC0CN0 Port Match P0 0 P1 7 P0MASK P0MAT P1MASK P1MAT Any pin used for GPIO P0 0 P2 6 P0SKIP P1S...

Page 97: ...the output characteristics of that pin and the dedicated function will only have input access Likewise it is possible for firmware to read the logic state of any digital I O pin as signed to a crossbar peripheral but the output state cannot be directly modified Figure 12 3 Crossbar Priority Decoder Example Assignments on page 96 shows an example of the resulting pin assignments of the device with ...

Page 98: ...available to the crossbar Note that this does not mean any peripheral can always be assigned to the highlighted pins The actual pin assignments are determined by the priority of the enabled peripherals EFM8SB2 Reference Manual Port I O Crossbar External Interrupts and Port Match silabs com Smart Connected Energy friendly Rev 0 1 97 ...

Page 99: ...kip the corresponding port pins Pins can be skipped by setting the corresponding bit in PnSKIP to 1 NSS is only pinned out when the SPI is in 4 wire mode XTAL2 XTAL1 CNVSTR VREF SPI1 SCK SPI1 MISO SPI1 MOSI SPI1 NSS SYSCLK PCA0 CEX0 PCA0 CEX1 PCA0 CEX2 SPI0 SCK SPI0 MISO SPI0 MOSI SPI0 NSS SMB0 SDA SMB0 SCL CMP0 CP0 CMP0 CP0A CMP1 CP1 CMP1 CP1A PCA0 CEX3 PCA0 CEX4 PCA0 CEX5 PCA0 ECI Timer0 T0 Time...

Page 100: ...recognized It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated 12 3 5 Port Match Port match functionality allows system events to be triggered by a logic value change on one or more port I O pins A software control led value stored in the PnMATCH registers specifies the expected or normal logic values of the associated ...

Page 101: ... pin 5 CP0AE 0 RW Comparator0 Asynchronous Output Enable Value Name Description 0 DISABLED Asynchronous CP0 unavailable at Port pin 1 ENABLED Asynchronous CP0 routed to Port pin 4 CP0E 0 RW Comparator0 Output Enable Value Name Description 0 DISABLED CP0 unavailable at Port pin 1 ENABLED CP0 routed to Port pin 3 SYSCKE 0 RW SYSCLK Output Enable Value Name Description 0 DISABLED SYSCLK unavailable a...

Page 102: ... The SPI can be assigned either 3 or 4 GPIO pins 0 URT0E 0 RW UART I O Output Enable Value Name Description 0 DISABLED UART I O unavailable at Port pin 1 ENABLED UART TX RX routed to Port pins P0 4 and P0 5 EFM8SB2 Reference Manual Port I O Crossbar External Interrupts and Port Match silabs com Smart Connected Energy friendly Rev 0 1 101 ...

Page 103: ... T1 routed to Port pin 4 T0E 0 RW T0 Enable Value Name Description 0 DISABLED T0 unavailable at Port pin 1 ENABLED T0 routed to Port pin 3 ECIE 0 RW PCA0 External Counter Input Enable Value Name Description 0 DISABLED ECI unavailable at Port pin 1 ENABLED ECI routed to Port pin 2 0 PCA0ME 0x0 RW PCA Module I O Enable Value Name Description 0x0 DISABLED All PCA I O unavailable at Port pins 0x1 CEX0...

Page 104: ...up Disable Value Name Description 0 PULL_UPS_ENABLED Weak Pullups enabled except for Ports whose I O are configured for analog mode 1 PULL_UPS_DISABLED Weak Pullups disabled 6 XBARE 0 RW Crossbar Enable Value Name Description 0 DISABLED Crossbar disabled 1 ENABLED Crossbar enabled 5 0 Reserved Must write reset value The Crossbar must be enabled XBARE 1 to use any port pin as a digital output EFM8S...

Page 105: ...ic value is compared to P0MAT 7 6 B6 0 RW Port 0 Bit 6 Mask Value See bit 7 description 5 B5 0 RW Port 0 Bit 5 Mask Value See bit 7 description 4 B4 0 RW Port 0 Bit 4 Mask Value See bit 7 description 3 B3 0 RW Port 0 Bit 3 Mask Value See bit 7 description 2 B2 0 RW Port 0 Bit 2 Mask Value See bit 7 description 1 B1 0 RW Port 0 Bit 1 Mask Value See bit 7 description 0 B0 0 RW Port 0 Bit 0 Mask Valu...

Page 106: ...ith logic HIGH 6 B6 1 RW Port 0 Bit 6 Match Value See bit 7 description 5 B5 1 RW Port 0 Bit 5 Match Value See bit 7 description 4 B4 1 RW Port 0 Bit 4 Match Value See bit 7 description 3 B3 1 RW Port 0 Bit 3 Match Value See bit 7 description 2 B2 1 RW Port 0 Bit 2 Match Value See bit 7 description 1 B1 1 RW Port 0 Bit 1 Match Value See bit 7 description 0 B0 1 RW Port 0 Bit 0 Match Value See bit ...

Page 107: ...atch See bit 7 description 4 B4 1 RW Port 0 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 0 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 0 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 0 Bit 1 Latch See bit 7 description 0 B0 1 RW Port 0 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading th...

Page 108: ... bit 7 description 5 B5 1 RW Port 0 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 0 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 0 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 0 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 0 Bit 1 Input Mode See bit 7 description 0 B0 1 RW Port 0 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have the...

Page 109: ...l 6 B6 0 RW Port 0 Bit 6 Output Mode See bit 7 description 5 B5 0 RW Port 0 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 0 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 0 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 0 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 0 Bit 1 Output Mode See bit 7 description 0 B0 0 RW Port 0 Bit 0 Output Mode See bit 7 description...

Page 110: ...pin is skipped by the crossbar 6 B6 0 RW Port 0 Bit 6 Skip See bit 7 description 5 B5 0 RW Port 0 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 0 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 0 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 0 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 0 Bit 1 Skip See bit 7 description 0 B0 0 RW Port 0 Bit 0 Skip See bit 7 description EFM8SB2 Reference M...

Page 111: ...output drive strength 1 HIGH_DRIVE P0 5 output has high output drive strength 4 B4 0 RW Port 0 Bit 4 Drive Strength Value Name Description 0 LOW_DRIVE P0 4 output has low output drive strength 1 HIGH_DRIVE P0 4 output has high output drive strength 3 B3 0 RW Port 0 Bit 3 Drive Strength Value Name Description 0 LOW_DRIVE P0 3 output has low output drive strength 1 HIGH_DRIVE P0 3 output has high ou...

Page 112: ...lue is ignored and will not cause a port mismatch event 1 COMPARED P1 7 pin logic value is compared to P1MAT 7 6 B6 0 RW Port 1 Bit 6 Mask Value See bit 7 description 5 B5 0 RW Port 1 Bit 5 Mask Value See bit 7 description 4 B4 0 RW Port 1 Bit 4 Mask Value See bit 7 description 3 B3 0 RW Port 1 Bit 3 Mask Value See bit 7 description 2 B2 0 RW Port 1 Bit 2 Mask Value See bit 7 description 1 B1 0 RW...

Page 113: ...ee bit 7 description 5 B5 1 RW Port 1 Bit 5 Match Value See bit 7 description 4 B4 1 RW Port 1 Bit 4 Match Value See bit 7 description 3 B3 1 RW Port 1 Bit 3 Match Value See bit 7 description 2 B2 1 RW Port 1 Bit 2 Match Value See bit 7 description 1 B1 1 RW Port 1 Bit 1 Match Value See bit 7 description 0 B0 1 RW Port 1 Bit 0 Match Value See bit 7 description Port 1 consists of 8 bits P1 0 P1 7 o...

Page 114: ...atch See bit 7 description 3 B3 1 RW Port 1 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 1 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 1 Bit 1 Latch See bit 7 description 0 B0 1 RW Port 1 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading this register returns the logic value at the pin rega...

Page 115: ... See bit 7 description 4 B4 1 RW Port 1 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 1 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 1 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 1 Bit 1 Input Mode See bit 7 description 0 B0 1 RW Port 1 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver d...

Page 116: ...ription 5 B5 0 RW Port 1 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 1 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 1 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 1 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 1 Bit 1 Output Mode See bit 7 description 0 B0 0 RW Port 1 Bit 0 Output Mode See bit 7 description Port 1 consists of 8 bits P1 0 P1 7 on QFN32 and L...

Page 117: ... 6 Skip See bit 7 description 5 B5 0 RW Port 1 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 1 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 1 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 1 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 1 Bit 1 Skip See bit 7 description 0 B0 0 RW Port 1 Bit 0 Skip See bit 7 description Port 1 consists of 8 bits P1 0 P1 7 on QFN32 and LQFP32 packages and 7...

Page 118: ...output drive strength 1 HIGH_DRIVE P1 5 output has high output drive strength 4 B4 0 RW Port 1 Bit 4 Drive Strength Value Name Description 0 LOW_DRIVE P1 4 output has low output drive strength 1 HIGH_DRIVE P1 4 output has high output drive strength 3 B3 0 RW Port 1 Bit 3 Drive Strength Value Name Description 0 LOW_DRIVE P1 3 output has low output drive strength 1 HIGH_DRIVE P1 3 output has high ou...

Page 119: ...ve low 1 HIGH P2 7 is high Set P2 7 to drive or float high 6 B6 1 RW Port 2 Bit 6 Latch See bit 7 description 5 B5 1 RW Port 2 Bit 5 Latch See bit 7 description 4 B4 1 RW Port 2 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 2 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 2 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 2 Bit 1 Latch See bit 7 description 0 B0 1 RW Port 2 Bit 0 Latch See bi...

Page 120: ...ode See bit 7 description 4 B4 1 RW Port 2 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 2 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 2 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 2 Bit 1 Input Mode See bit 7 description 0 B0 1 RW Port 2 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have their weak pullup digital driver and digital receive...

Page 121: ...escription 5 B5 0 RW Port 2 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 2 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 2 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 2 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 2 Bit 1 Output Mode See bit 7 description 0 B0 0 RW Port 2 Bit 0 Output Mode See bit 7 description Port 2 consists of 8 bits P2 0 P2 7 on QFN32 an...

Page 122: ...Bit 6 Skip See bit 7 description 5 B5 0 RW Port 2 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 2 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 2 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 2 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 2 Bit 1 Skip See bit 7 description 0 B0 0 RW Port 2 Bit 0 Skip See bit 7 description Port 2 consists of 8 bits P2 0 P2 7 on QFN32 and LQFP32 packages an...

Page 123: ...output drive strength 1 HIGH_DRIVE P2 5 output has high output drive strength 4 B4 0 RW Port 2 Bit 4 Drive Strength Value Name Description 0 LOW_DRIVE P2 4 output has low output drive strength 1 HIGH_DRIVE P2 4 output has high output drive strength 3 B3 0 RW Port 2 Bit 3 Drive Strength Value Name Description 0 LOW_DRIVE P2 3 output has low output drive strength 1 HIGH_DRIVE P2 3 output has high ou...

Page 124: ...ption 0 LOW_DRIVE P2 0 output has low output drive strength 1 HIGH_DRIVE P2 0 output has high output drive strength Port 2 consists of 8 bits P2 0 P2 7 on QFN32 and LQFP32 packages and 1 bit P2 7 on QFN24 packages EFM8SB2 Reference Manual Port I O Crossbar External Interrupts and Port Match silabs com Smart Connected Energy friendly Rev 0 1 123 ...

Page 125: ...cted pin Value Name Description 0x0 P0_0 Select P0 0 0x1 P0_1 Select P0 1 0x2 P0_2 Select P0 2 0x3 P0_3 Select P0 3 0x4 P0_4 Select P0 4 0x5 P0_5 Select P0 5 0x6 P0_6 Select P0 6 0x7 P0_7 Select P0 7 3 IN0PL 0 RW INT0 Polarity Value Name Description 0 ACTIVE_LOW INT0 input is active low 1 ACTIVE_HIGH INT0 input is active high 2 0 IN0SL 0x1 RW INT0 Port Pin Selection These bits select which port pi...

Page 126: ...x3 P0_3 Select P0 3 0x4 P0_4 Select P0 4 0x5 P0_5 Select P0 5 0x6 P0_6 Select P0 6 0x7 P0_7 Select P0 7 EFM8SB2 Reference Manual Port I O Crossbar External Interrupts and Port Match silabs com Smart Connected Energy friendly Rev 0 1 125 ...

Page 127: ...al reference sources ADC0 External Pins SAR Analog to Digital Converter Accumulator Window Compare SYSCLK Clock Divider Less Than Greater Than Control Configuration ADC0 VDD VREF Internal LDO Trigger Selection ADWINT Window Interrupt SAR clock Temp Sensor VDD GND Internal LDO Input Multiplexer Selection ADBUSY On Demand Timer 0 Overflow Timer 2 Overflow Timer 3 Overflow CNVSTR External Pin ADINT I...

Page 128: ...e REFSL field selects be tween the different reference options while GNDSL configures the ground connection 13 3 2 1 Internal Voltage Reference The high speed internal reference is self contained and stabilized It is not routed to an external pin and requires no external decou pling When selected the internal reference will be automatically enabled disabled on an as needed basis by the ADC The ref...

Page 129: ...llows selection of external pins the on chip temperature sensor the internal regulated sup ply the VDD supply or GND ADC input channels are selected using the ADC0MX register Note Any port pins selected as ADC inputs should be configured as analog inputs in their associated port configuration register and configured to be skipped by the crossbar 13 3 3 1 Multiplexer Channel Selection Table 13 1 AD...

Page 130: ...a 1 to the ADBUSY bit initiates the conversion 2 Hardware triggered An automatic internal event such as a timer overflow initiates the conversion 3 External pin triggered A rising edge on the CNVSTR input signal initiates the conversion Writing a 1 to ADBUSY provides software control of ADC0 whereby conversions are performed on demand All other trigger sources occur autonomous to code execution Wh...

Page 131: ...MPLE depends on the PGA gain See the electrical specifications for details Figure 13 2 ADC Eqivalent Input Circuit The required ADC0 settling time for a given settling accuracy SA may be approximated as follows t ln 2n SA x RTOTAL x CSAMPLE Where SA is the settling accuracy given as a fraction of an LSB for example 0 25 to settle within 1 4 LSB t is the required settling time in seconds RTOTAL is ...

Page 132: ... for External Trigger Source SAR Clocks Track or Convert Convert Track ADTM 0 Track Convert Low Power Mode Low Power or Convert 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Figure 13 3 Track and Conversion Example Timing Normal Non Burst Operation When burst mode is enabled additional tracking times may need to be specified Because burst mode may pow...

Page 133: ...ower state i e the state the ADC enters when not tracking or performing conversions If ADEN is set to logic 0 the ADC is powered down after each burst If AD EN is set to logic 1 the ADC remains enabled after each burst On each convert start signal the ADC is awakened from its idle power state If the ADC is powered down it will automatically power up and wait for the amount of time programmed to th...

Page 134: ...L registers are set to 0 The exam ple below shows the right justified result for various input voltages and repeat counts Notice that accumulating 2n samples is equiva lent to left shifting by n bit positions when all samples returned from the ADC have the same value Table 13 3 Effects of ADRPT on Output Code Input Voltage Repeat Count 4 Repeat Count 16 Repeat Count 64 VREF x 1023 1024 0x0FFC 0x3F...

Page 135: ...how how the ADC0GT and ADC0LT registers may be configured to set the ADWINT flag when the ADC output code is above below beween or outside of specific values Table 13 5 ADC Window Comparator Example Above 0x0080 Comparison Register Settings Output Code ADC0H L ADWINT Effects 0x03FF ADWINT 1 0x0081 ADC0GTH L 0x0080 0x0080 ADWINT Not Affected 0x007F 0x0001 ADC0LTH L 0x0000 0x0000 Table 13 6 ADC Wind...

Page 136: ...ator Example Outside the 0x0040 to 0x0080 range Comparison Register Settings Output Code ADC0H L ADWINT Effects 0x03FF ADWINT 1 0x0081 ADC0GTH L 0x0080 0x0080 ADWINT Not Affected 0x007F 0x0041 ADC0LTH L 0x0040 0x0040 0x003F ADWINT 1 0x0000 EFM8SB2 Reference Manual Analog to Digital Converter ADC0 silabs com Smart Connected Energy friendly Rev 0 1 135 ...

Page 137: ...librated temperature sensor output is extremely linear and suitable for relative temperature measurements For absolute tem perature measurements offset and or gain calibration is recommended Typically a 1 point offset calibration includes the following steps 1 Control measure the ambient temperature this temperature must be known 2 Power the device and delay for a few seconds to allow for self hea...

Page 138: ...tes an ADC conversion when ADCM 000 This bit should not be polled to indicate when a conver sion is complete Instead the ADINT bit should be used when polling for conversion completion 3 ADWINT 0 RW Window Compare Interrupt Flag Set by hardware when the contents of ADC0H ADC0L fall within the window specified by ADC0GTH ADC0GTL and ADC0LTH ADC0LTL Can trigger an interrupt Must be cleared by firmwa...

Page 139: ...it Mode Enable Value Name Description 0 NORMAL ADC0 operates in 10 bit mode normal operation 1 8_BIT ADC0 operates in 8 bit mode 1 ADTM 0 RW Track Mode Selects between Normal or Delayed Tracking Modes Value Name Description 0 TRACK_NORMAL Normal Track Mode When ADC0 is enabled conversion begins immediately fol lowing the start of conversion signal 1 TRACK_DELAYED Delayed Track Mode When ADC0 is en...

Page 140: ...ll remaining bit combinations are reserved Value Name Description 0x0 RIGHT_NO_SHIFT Right justified No shifting applied 0x1 RIGHT_SHIFT_1 Right justified Shifted right by 1 bit 0x2 RIGHT_SHIFT_2 Right justified Shifted right by 2 bits 0x3 RIGHT_SHIFT_3 Right justified Shifted right by 3 bits 0x4 LEFT_NO_SHIFT Left justified No shifting applied 2 0 ADRPT 0x0 RW Repeat Count Selects the number of c...

Page 141: ...cutive conversions performed in Burst Mode When ADTM is set an additional 3 SARCLKs are added to this time Tbmtk 64 ADTK Fhfosc The Burst Mode track delay is not inserted prior to the first conversion The required tracking time for the first conversion should be defined with the ADPWR field 13 4 6 ADC0H ADC0 Data Word High Byte Bit 7 6 5 4 3 2 1 0 Name ADC0H Access RW Reset 0x00 SFR Page 0x0 SFR A...

Page 142: ... 8 ADC0GTH ADC0 Greater Than High Byte Bit 7 6 5 4 3 2 1 0 Name ADC0GTH Access RW Reset 0xFF SFR Page 0x0 SFR Address 0xC4 Bit Name Reset Access Description 7 0 ADC0GTH 0xFF RW Greater Than High Byte Most significant byte of the 16 bit greater than window compare register 13 4 9 ADC0GTL ADC0 Greater Than Low Byte Bit 7 6 5 4 3 2 1 0 Name ADC0GTL Access RW Reset 0xFF SFR Page 0x0 SFR Address 0xC3 B...

Page 143: ... Reserved ADC0MX Access R RW Reset 0x0 0x1F SFR Page 0x0 SFR Address 0xBB Bit Name Reset Access Description 7 5 Reserved Must write reset value 4 0 ADC0MX 0x1F RW AMUX0 Positive Input Selection Selects the positive input channel for ADC0 For reserved bit combinations no input is selected Before switching the ADC multiplexer from another channel to the temperature sensor the ADC mux should select t...

Page 144: ...VDD pin 0x2 INTERNAL_LDO The ADC0 voltage reference is the internal 1 8 V digital supply voltage 0x3 HIGH_SPEED_VREF The ADC0 voltage reference is the internal 1 65 V high speed voltage reference 2 TEMPE 0 RW Temperature Sensor Enable Enables Disables the internal temperature sensor Value Name Description 0 TEMP_DISABLED Disable the Temperature Sensor 1 TEMP_ENABLED Enable the Temperature Sensor 1...

Page 145: ...offset measurement 13 4 15 TOFFL Temperature Sensor Offset Low Bit 7 6 5 4 3 2 1 0 Name TOFF Reserved Access R R Reset Varies 0x00 SFR Page 0xF SFR Address 0x85 Bit Name Reset Access Description 7 6 TOFF Varies R Temperature Sensor Offset Low Least Significant Bits of the 10 bit temperature sensor offset measurement 5 0 Reserved Must write reset value EFM8SB2 Reference Manual Analog to Digital Con...

Page 146: ...ble of sourcing or sinking current in programmable steps Two operational modes Low Power Mode and High Current Mode 14 3 Functional Description 14 3 1 Overview The programmable current reference IREF0 generates a current output in either source or sink mode Each mode has two output current settings Low Power Mode and High Current Mode The maximum current output in Low Power Mode is 63 µA 1 µA step...

Page 147: ...IREF0 is a current sink 6 MDSEL 0 RW IREF0 Output Mode Select Selects Low Power or High Current Mode Value Name Description 0 LOW_POWER Low Current Mode is selected step size 1 uA 1 HIGH_CURRENT High Current Mode is selected step size 8 uA 5 0 IREF0DAT 0x00 RW IREF0 Data Word Specifies the number of steps required to achieve the desired output current Output current direction x step size x IREF0DA...

Page 148: ...nous CPnA asynchronous SYSCLK GND Port Pins Negative Input Selection Port Pins Positive Input Selection Internal LDO Figure 15 1 Comparator Block Diagram 15 2 Features The comparator module includes the following features Up to 12 external positive inputs Up to 11 external negative inputs Additional input options Capacitive Sense Comparator output VDD VDD divided by 2 Internal connection to LDO ou...

Page 149: ... is determined by the settings of the CPHYN bits Settings of 20 10 or 5 mV nominal of nega tive hysteresis can be programmed or negative hysteresis can be disabled In a similar way the amount of positive hysteresis is deter mined by the setting the CPHYP bits CPn Positive programmable hysteresis CPHYP CPn Negative programmable hysteresis CPHYN CP0 out Figure 15 2 Comparator Hysteresis Plot 15 3 3 ...

Page 150: ...Compare 1101 CMP0P 13 VDD_DIV_2 VDD divided by 2 1110 CMP0P 14 VDD VDD Supply Voltage 1111 CMP0P 15 VDD2 VDD Supply Voltage Table 15 2 CMP0 Negative Input Multiplexer Channels CMXN Setting in Register CMP0MX Signal Name Enumeration Name QFP32 Pin Name QFN32 Pin Name QFN24 Pin Name 0000 CMP0N 0 CMP0N0 P0 1 P0 1 P0 1 0001 CMP0N 1 CMP0N1 P0 3 P0 3 P0 3 0010 CMP0N 2 CMP0N2 P0 5 P0 5 P0 5 0011 CMP0N 3 ...

Page 151: ... 0 Reserved 1001 CMP1P 9 CMP1P9 P2 2 P2 2 Reserved 1010 CMP1P 10 CMP1P10 P2 4 P2 4 Reserved 1011 CMP1P 11 CMP1P11 P2 6 P2 6 Reserved 1100 CMP1P 12 CS_COMPARE Capacitive Sense Compare 1101 CMP1P 13 VDD_DIV_2 VDD divided by 2 1110 CMP1P 14 VDD2 VDD Supply Voltage 1111 CMP1P 15 VDD VDD Supply Voltage Table 15 4 CMP1 Negative Input Multiplexer Channels CMXN Setting in Register CMP1MX Signal Name Enume...

Page 152: ...When disabled the comparator output if assigned to a port I O pin via the crossbar defaults to the logic low state and the power supply to the comparator is turned off Comparator interrupts can be generated on both rising edge and falling edge output transitions The CPFIF flag is set to logic 1 upon a comparator falling edge occurrence and the CPRIF flag is set to logic 1 upon the comparator risin...

Page 153: ..._SET No comparator rising edge has occurred since this flag was last cleared 1 RISING_EDGE Comparator rising edge has occurred 4 CPFIF 0 RW Comparator Falling Edge Flag Must be cleared by firmware Value Name Description 0 NOT_SET No comparator falling edge has occurred since this flag was last cleared 1 FALLING_EDGE Comparator falling edge has occurred 3 2 CPHYP 0x0 RW Comparator Positive Hysteres...

Page 154: ...tion 0 RISE_INT_DISABLED Comparator rising edge interrupt disabled 1 RISE_INT_ENABLED Comparator rising edge interrupt enabled 4 CPFIE 0 RW Comparator Falling Edge Interrupt Enable Value Name Description 0 FALL_INT_DISABLED Comparator falling edge interrupt disabled 1 FALL_INT_ENABLED Comparator falling edge interrupt enabled 3 2 Reserved Must write reset value 1 0 CPMD 0x2 RW Comparator Mode Sele...

Page 155: ...set Access Description 7 4 CMXN 0xF RW Comparator Negative Input MUX Selection This field selects the negative input for the comparator 3 0 CMXP 0xF RW Comparator Positive Input MUX Selection This field selects the positive input for the comparator EFM8SB2 Reference Manual Comparators CMP0 and CMP1 silabs com Smart Connected Energy friendly Rev 0 1 154 ...

Page 156: ..._SET No comparator rising edge has occurred since this flag was last cleared 1 RISING_EDGE Comparator rising edge has occurred 4 CPFIF 0 RW Comparator Falling Edge Flag Must be cleared by firmware Value Name Description 0 NOT_SET No comparator falling edge has occurred since this flag was last cleared 1 FALLING_EDGE Comparator falling edge has occurred 3 2 CPHYP 0x0 RW Comparator Positive Hysteres...

Page 157: ...tion 0 RISE_INT_DISABLED Comparator rising edge interrupt disabled 1 RISE_INT_ENABLED Comparator rising edge interrupt enabled 4 CPFIE 0 RW Comparator Falling Edge Interrupt Enable Value Name Description 0 FALL_INT_DISABLED Comparator falling edge interrupt disabled 1 FALL_INT_ENABLED Comparator falling edge interrupt enabled 3 2 Reserved Must write reset value 1 0 CPMD 0x2 RW Comparator Mode Sele...

Page 158: ...set Access Description 7 4 CMXN 0xF RW Comparator Negative Input MUX Selection This field selects the negative input for the comparator 3 0 CMXP 0xF RW Comparator Positive Input MUX Selection This field selects the positive input for the comparator EFM8SB2 Reference Manual Comparators CMP0 and CMP1 silabs com Smart Connected Energy friendly Rev 0 1 157 ...

Page 159: ...00 or 0xFFFFFFFF Automatic flash read control 8 8 8 Flash Memory CRC0FLIP 8 8 8 8 8 Figure 16 1 CRC Functional Block Diagram 16 2 Features The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols The CRC module includes the following features Support for CCITT 16 polynomial 0x1021 Support for CRC 32 polynomial 0x04C11DB7 Byte level bit ...

Page 160: ...vidend for polynomial arithmetic binary arithmetic with no carries CRC_acc CRC_acc CRC_input 8 Divide the poly into the dividend using CRC XOR subtraction CRC_acc holds the remainder of each divide Only complete this division for 8 bits since input is 1 byte for i 0 i 8 i Check if the MSB is set if MSB is 1 then the POLY can divide into the dividend if CRC_acc 0x8000 0x8000 if so shift the CRC val...

Page 161: ... for polynomial arithmetic binary arithmetic with no carries CRC_acc CRC_acc CRC_input Divide the poly into the dividend using CRC XOR subtraction CRC_acc holds the remainder of each divide Only complete this division for 8 bits since input is 1 byte for i 0 i 8 i Check if the LSB is set if LSB is 1 then the POLY can divide into the dividend if CRC_acc 0x00000001 0x00000001 if so shift the CRC val...

Page 162: ...alue after each read 16 3 5 Using the CRC to Check Code Memory The CRC module may be configured to automatically perform a CRC on one or more blocks of code memory To perform a CRC on code contents 1 Select the initial result value using CRCVAL 2 Set the result to its initial value write 1 to CRCINIT 3 Write the high byte of the starting address to the CRCST bit field 4 Set the AUTOEN bit to 1 5 W...

Page 163: ... 0x0 RW CRC Result Pointer Specifies the byte of the CRC result to be read written on the next access to CRC0DAT The value of these bits will auto increment upon each read or write Value Name Description 0x0 ACCESS_B0 CRC0DAT accesses bits 7 0 of the 16 bit or 32 bit CRC result 0x1 ACCESS_B1 CRC0DAT accesses bits 15 8 of the 16 bit or 32 bit CRC result 0x2 ACCESS_B2 CRC0DAT accesses bits 7 0 of th...

Page 164: ...should be performed before reading CRC0DAT 16 4 4 CRC0AUTO CRC0 Automatic Control Bit 7 6 5 4 3 2 1 0 Name AUTOEN CRCDN CRCST Access RW RW RW Reset 0 1 0x00 SFR Page 0xF SFR Address 0x96 Bit Name Reset Access Description 7 AUTOEN 0 RW Automatic CRC Calculation Enable When AUTOEN is set to 1 any write to CRC0CN0 will initiate an automatic CRC starting at flash sector CRCST and con tinuing for CRCCN...

Page 165: ...e automatic CRC calculation is CRCST CRCCNT x Block Size 1 The block size is 1024 bytes 16 4 6 CRC0FLIP CRC0 Bit Flip Bit 7 6 5 4 3 2 1 0 Name CRC0FLIP Access RW Reset 0x00 SFR Page 0xF SFR Address 0x95 Bit Name Reset Access Description 7 0 CRC0FLIP 0x00 RW CRC0 Bit Flip Any byte written to CRC0FLIP is read back in a bit reversed order i e the written LSB becomes the MSB For example If 0xC0 is wri...

Page 166: ...bar to port I O when enabled Channel 5 WDT Mode Control Capture Compare Channel 4 Mode Control Capture Compare PCA0 ECI CEX3 EXTCLK 8 Timer 0 Overflow SYSCLK SYSCLK 4 SYSCLK 12 Control Configuration Output Drive Logic PCA Counter Channel 3 Mode Control Capture Compare CEX4 CEX5 Interrupt Logic Sync Sync SYSCLK Channel 2 Mode Control Capture Compare Channel 1 Mode Control Capture Compare Channel 0 ...

Page 167: ...rrupt Sources The PCA0 module shares one interrupt vector among all of its modules There are are several event flags that can be used to generate a PCA0 interrupt They are as follows the main PCA counter overflow flag CF which is set upon a 16 bit overflow of the PCA0 coun ter an intermediate overflow flag COVF which can be set on an overflow from the 8th 11th bit of the PCA0 counter and the indiv...

Page 168: ...0 E 0 1 A D X B X 3 16 Bit Pulse Width Modulator 1 C 0 0 E 0 1 A 0 X B X X Notes 1 X Don t Care no functional difference for individual module if 1 or 0 2 A Enable interrupts for this module PCA interrupt triggered on CCFn set to 1 3 B Enable 8th 11th bit overflow interrupt Depends on setting of CLSEL 4 C When set to 0 the digital comparator is off For high speed and frequency output modes the ass...

Page 169: ... interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not auto matically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software If both CAPPn and CAPNn bits are set to logic 1 then the state of the port pin associated with CEXn can be read directly to determine whether a rising edge or falling edge caused...

Page 170: ...rrupt service routine and it must be cleared by software Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode Note When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 PCA0L PCA0CPLn PCA0H PCA0CPHn ECOMn Compare Enable PCA Clock ...

Page 171: ... software Setting the TOGn MATn and ECOMn bits in the PCA0CPMn register enables the High Speed Output mode If ECOMn is cleared the associated pin retains its state and not toggle on the next match event Note When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 ...

Page 172: ... register Note The MATn bit should normally be set to 0 in this mode If the MATn bit is set to 1 the CCFn flag for the channel will be set when the 16 bit PCA0 counter and the 16 bit capture compare register for the channel are equal PCA0L ECOMn Compare Enable PCA Clock 8 bit Comparator match Toggle TOGn Toggle Enable CEXn 8 bit Adder Adder Enable PCA0CPLn PCA0CPHn Figure 17 5 PCA Frequency Output...

Page 173: ...les configured for edge aligned mode at the same resolution align on the overflow edge of the waveforms An example of the PWM timing in edge aligned mode for two channels is shown here 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 Counter PCA0 0x0001 Capture Compare PCA0CP0 Output CEX0 PCA Clock match edge overflow edge 0x0005 Capture Compare PCA0CP1 Output CEX1 match edge Figure 17 6 Edge Alig...

Page 174: ... The data written to define the duty cycle should be right justified in the registers The auto reload registers are accessed read or written when the bit AR SEL in PCA0PWM is set to 1 The capture compare registers are accessed when ARSEL is set to 0 This allows seamless updating of the PWM waveform as the PCA0CPn register is reloaded automatically with the value stored in the auto reload registers...

Page 175: ...er will run until the WDT is disabled The PCA counter run control bit CR will read zero if the WDT is enabled but user software has not enabled the PCA counter If a match occurs between PCA0CPH5 and PCA0H while the WDT is enabled a reset will be generated To prevent a WDT reset the WDT may be updated with a write of any value to PCA0CPH5 Upon a PCA0CPH5 write PCA0H plus the offset held in PCA0CPL5...

Page 176: ...stem reset If WDLCK is not set the WDT is disabled by clearing the WDTE bit The WDT is enabled following any reset The PCA0 counter clock defaults to the system clock divided by 12 PCA0L defaults to 0x00 and PCA0CPL2 defaults to 0x00 This results in a WDT timeout interval of 256 PCA clock cycles or 3072 system clock cycles lists some example timeout intervals for typical system clocks Table 17 3 W...

Page 177: ...U to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by firmware 3 CCF3 0 RW PCA Module 3 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF3 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware ...

Page 178: ...ks unlocks the Watchdog Timer Enable When WDLCK is set the Watchdog Timer may not be disabled until the next system reset Value Name Description 0 UNLOCKED Watchdog Timer Enable unlocked 1 LOCKED Watchdog Timer Enable locked 4 Reserved Must write reset value 3 1 CPS 0x0 RW PCA Counter Timer Pulse Select These bits select the timebase source for the PCA counter Value Name Description 0x0 SYSCLK_DIV...

Page 179: ...ter Timer Overflow interrupt request when CF is set When the WDTE bit is set to 1 the other bits in the PCA0MD register cannot be modified To change the contents of the PCA0MD register the Watchdog Timer must first be disabled EFM8SB2 Reference Manual Programmable Counter Array PCA0 silabs com Smart Connected Energy friendly Rev 0 1 178 ...

Page 180: ...te PCA interrupts 1 COVF_MASK_ENA BLED A PCA interrupt will be generated when COVF is set 5 COVF 0 RW Cycle Overflow Flag This bit indicates an overflow of the 8th to 11th bit of the main PCA counter PCA0 The specific bit used for this flag de pends on the setting of the Cycle Length Select bits The bit can be set by hardware or firmware but must be cleared by firmware Value Name Description 0 NO_...

Page 181: ...Timer High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0H Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xFA Bit Name Reset Access Description 7 0 PCA0H 0x00 RW PCA Counter Timer High Byte The PCA0H register holds the high byte MSB of the 16 bit PCA Counter Timer Reads of this register will read the con tents of a snapshot register whose contents are updated only when the contents of PCA0L are read When the ...

Page 182: ... a module s capture compare register cause the CCF0 bit in the PCA0MD register to be set to logic 1 2 TOG 0 RW Channel 0 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX0 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Cha...

Page 183: ...ter will clear the module s ECOM bit to a 0 17 4 8 PCA0CPH0 PCA Channel 0 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPH0 Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xFC Bit Name Reset Access Description 7 0 PCA0CPH 0 0x00 RW PCA Channel 0 Capture Module High Byte The PCA0CPH0 register holds the high byte MSB of the 16 bit capture module This register address also allows access to th...

Page 184: ... a module s capture compare register cause the CCF1 bit in the PCA0MD register to be set to logic 1 2 TOG 0 RW Channel 1 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX1 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Cha...

Page 185: ...ter will clear the module s ECOM bit to a 0 17 4 11 PCA0CPH1 PCA Channel 1 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPH1 Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xEA Bit Name Reset Access Description 7 0 PCA0CPH 1 0x00 RW PCA Channel 1 Capture Module High Byte The PCA0CPH1 register holds the high byte MSB of the 16 bit capture module This register address also allows access to t...

Page 186: ...h a module s capture compare register cause the CCF2 bit in the PCA0MD register to be set to logic 1 2 TOG 0 RW Channel 2 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX2 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Ch...

Page 187: ...ter will clear the module s ECOM bit to a 0 17 4 14 PCA0CPH2 PCA Channel 2 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPH2 Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xEC Bit Name Reset Access Description 7 0 PCA0CPH 2 0x00 RW PCA Channel 2 Capture Module High Byte The PCA0CPH2 register holds the high byte MSB of the 16 bit capture module This register address also allows access to t...

Page 188: ...h a module s capture compare register cause the CCF3 bit in the PCA0MD register to be set to logic 1 2 TOG 0 RW Channel 3 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX3 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Ch...

Page 189: ...ter will clear the module s ECOM bit to a 0 17 4 17 PCA0CPH3 PCA Channel 3 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPH3 Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xEE Bit Name Reset Access Description 7 0 PCA0CPH 3 0x00 RW PCA Channel 3 Capture Module High Byte The PCA0CPH3 register holds the high byte MSB of the 16 bit capture module This register address also allows access to t...

Page 190: ...h a module s capture compare register cause the CCF4 bit in the PCA0MD register to be set to logic 1 2 TOG 0 RW Channel 4 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX4 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Ch...

Page 191: ...ter will clear the module s ECOM bit to a 0 17 4 20 PCA0CPH4 PCA Channel 4 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPH4 Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xFE Bit Name Reset Access Description 7 0 PCA0CPH 4 0x00 RW PCA Channel 4 Capture Module High Byte The PCA0CPH4 register holds the high byte MSB of the 16 bit capture module This register address also allows access to t...

Page 192: ...h a module s capture compare register cause the CCF5 bit in the PCA0MD register to be set to logic 1 2 TOG 0 RW Channel 5 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX5 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Ch...

Page 193: ...ter will clear the module s ECOM bit to a 0 17 4 23 PCA0CPH5 PCA Channel 5 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPH5 Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xD3 Bit Name Reset Access Description 7 0 PCA0CPH 5 0x00 RW PCA Channel 5 Capture Module High Byte The PCA0CPH5 register holds the high byte MSB of the 16 bit capture module This register address also allows access to t...

Page 194: ...IF_AD7 Mode Timing Control External RAM XRAM EMIF_AD6 EMIF_AD0 EMIF_A15 EMIF_A14 EMIF_A8 EMIF_RDb EMIF_ALEm EMIF_WRb Figure 18 1 EMIF Block Diagram 18 2 Features Supports multiplexed memory access Four external memory modes Internal only Split mode without bank select Split mode with bank select External only Configurable ALE address latch enable timing Configurable address setup and hold times Co...

Page 195: ...nals to the associated port pins In most configurations the RDb WRb and ALEm pins need to be skipped in the Crossbar to ensure they are controlled by their port latches The External Memory Interface claims the associated port pins for memory operations only during the execution of an off chip MOVX instruction Once the MOVX instruction has completed control of the Port pins reverts to the Port latc...

Page 196: ...7 P1 7 Not Available A8m Address Bit 8 P2 0 P2 0 Not Available A9m Address Bit 9 P2 1 P2 1 Not Available A10m Address Bit 10 P2 2 P2 2 Not Available A11m Address Bit 11 P2 3 P2 3 Not Available Note 1 EFM8SB2 devices support only multiplexed EMIF modes 2 EFM8SB2 devices support up to 12 address lines EFM8SB2 Reference Manual External Memory Interface EMIF0 silabs com Smart Connected Energy friendly...

Page 197: ...equivalent logic gate can be used to hold the lower 8 bits of the RAM address during the second half of the memory cycle when the address data bus contains data The external latch controlled by the ALEm Ad dress Latch Enable signal is automatically driven by the External Memory Interface logic An example SRAM interface showing multi plexed to non multiplexed conversion is shown in below This examp...

Page 198: ...Split Mode without Bank Select Split Mode with Bank Select External Only Timing diagrams for the different modes can be found in the Multiplexed Mode Section On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM Off Chip Memory Off Chip Memory Off Chip Memory On Chip XRAM 0xFFFF 0x0000 Internal Only 0xFFFF 0x0000 Split Mode without Bank Select 0xFFFF 0x0000 0xF...

Page 199: ...r off chip and unlike 8 bit MOVX operations the full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction Split Mode with Bank Select In Split Mode with Bank Select the XRAM memory map is split into two areas on chip space and off chip space Effective addresses below the on chip XRAM boundary will access on chip XRAM space Effective addresses above the on chip XRAM boundary...

Page 200: ...refore the minimum execution time of an off chip XRAM operation in multiplexed mode is 7 SYSCLK cycles 2 SYSCLKs for ALEm 1 for RDb or WRb 4 SYSCLKs The programmable setup and hold times default to the maxi mum delay settings after a reset Table 18 2 External Memory Interface Timing Parameter Description Min Max Units TACS Address Control Setup Time 0 3 x TSYSCLK ns TACW Address Control Pulse Widt...

Page 201: ...Db ALEm WRb RDb ALEm T ACH T WDH T ACW T ACS T WDS EMIF Address 8 MSBs from DPH EMIF Write Data EMIF Address 8 LSBs from DPL T ALEH T ALEL AD 7 0 m A 15 8 m AD 7 0 m A 15 8 m RDb WRb ALEm RDb WRb ALEm T ACH T ACW T ACS EMIF Address 8 MSBs from DPH EMIF Address 8 LSBs from DPL T ALEH T ALEL T RDH T RDS EMIF Read Data Muxed 16 bit Write Muxed 16 bit Read Figure 18 5 Multiplexed 16 bit MOVX Timing EF...

Page 202: ...PIO AD 7 0 m A 15 8 m RDb WRb ALEm RDb WRb ALEm T ACH T ACW T ACS EMIF Address 8 LSBs from R0 or R1 T ALEH T ALEL T RDH T RDS EMIF Read Data Muxed 8 bit Write Without Bank Select Muxed 8 bit Read Without Bank Select A 15 8 m A 15 8 m Figure 18 6 Multiplexed 8 bit MOVX without Bank Select Timing EFM8SB2 Reference Manual External Memory Interface EMIF0 silabs com Smart Connected Energy friendly Rev ...

Page 203: ...AD 7 0 m A 15 8 m RDb WRb ALEm RDb WRb ALEm T ACH T ACW T ACS EMIF Address 8 MSBs from EMI0CN EMIF Address 8 LSBs from R0 or R1 T ALEH T ALEL T RDH T RDS EMIF Read Data Muxed 8 bit Write with Bank Select Muxed 8 bit Read with Bank Select Figure 18 7 Multiplexed 8 bit MOVX with Bank Select Timing EFM8SB2 Reference Manual External Memory Interface EMIF0 silabs com Smart Connected Energy friendly Rev...

Page 204: ...st write reset value 4 0 PGSEL 0x00 RW XRAM Page Select The XRAM Page Select field provides the high byte of the 16 bit external data memory address when using an 8 bit MOVX command effectively selecting a 256 byte page of RAM 0x00 0x0000 to 0x00FF 0x01 0x0100 to 0x01FF 0xFE 0xFE00 to 0xFEFF 0xFF 0xFF00 to 0xFFFF EFM8SB2 Reference Manual External Memory Interface EMIF0 silabs com Smart Connected E...

Page 205: ... be set to a page that is not contained in the on chip address space 0x2 SPLIT_WITH_BANK_S ELECT Split Mode with Bank Select Accesses below the internal XRAM boundary are di rected on chip Accesses above the internal XRAM boundary are directed off chip 8 bit off chip MOVX operations uses the contents of EMI0CN to determine the high byte of the address 0x3 EXTERNAL_ONLY External Only MOVX accesses ...

Page 206: ...4 5_CLOCKS WR and RD pulse width is 5 SYSCLK cycles 0x5 6_CLOCKS WR and RD pulse width is 6 SYSCLK cycles 0x6 7_CLOCKS WR and RD pulse width is 7 SYSCLK cycles 0x7 8_CLOCKS WR and RD pulse width is 8 SYSCLK cycles 0x8 9_CLOCKS WR and RD pulse width is 9 SYSCLK cycles 0x9 10_CLOCKS WR and RD pulse width is 10 SYSCLK cycles 0xA 11_CLOCKS WR and RD pulse width is 11 SYSCLK cycles 0xB 12_CLOCKS WR and...

Page 207: ...Bit Name Reset Access Description 0x3 3_CLOCKS Address hold time 3 SYSCLK cycles EFM8SB2 Reference Manual External Memory Interface EMIF0 silabs com Smart Connected Energy friendly Rev 0 1 206 ...

Page 208: ...put in master mode or disabled to reduce the number of pins required Additional general purpose port I O pins can be used to select multiple slave devices in master mode SPI0 Shift Register MISO MOSI Clock Rate Generator SYSCLK Bus Control Master or Slave SCK Polarity SCK Phase NSS Control SCK NSS SPI0DAT TX Buffer RX Buffer Figure 19 1 SPI Block Diagram 19 2 Features The SPI module includes the f...

Page 209: ...n of the slave select NSS signal is dependent on the setting of the NSSMD bitfield There are three possible modes that can be selected with these bits NSSMD 1 0 00 3 Wire Master or 3 Wire Slave Mode The SPI operates in 3 wire mode and NSS is disabled When operating as a slave device the SPI is always selected in 3 wire mode Since no select signal is present the SPI must be the only slave on the bu...

Page 210: ...perate as a SPI slave As a slave bytes are shifted in through the MOSI pin and out through the MISO pin by an external master device controlling the SCK signal A bit counter in the SPI logic counts SCK edges When 8 bits have been shifted through the shift register a byte is copied into the receive buffer Data is read from the receive buffer by reading SPInDAT A slave device cannot initiate transfe...

Page 211: ...g the clock phase or polarity Note that CKPHA should be set to 0 on both the master and slave SPI when communicating between two Silicon Labs devices SCK CKPOL 0 CKPHA 0 SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 CKPHA 0 SCK CKPOL 1 CKPHA 1 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO MOSI Figure 19 5 Master Mode Data Clock Timing MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode MSB B...

Page 212: ...master transfer follows 1 Write the data to be sent to SPInDAT The transfer will begin on the bus at this time 2 Wait for the SPIF flag to generate an interrupt or poll SPIF until it is set to 1 3 Read the received data from SPInDAT 4 Clear the SPIF flag to 0 5 Repeat the sequence for any additional transfers Slave Transfers As a SPI slave the transfers are initiated by an external master device d...

Page 213: ... CKPOL 1 T MIH Figure 19 8 SPI Master Timing CKPHA 0 SCK T MCKH T MCKL MISO T MIH MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIS Figure 19 9 SPI Master Timing CKPHA 1 EFM8SB2 Reference Manual Serial Peripheral Interfaces SPI0 and SPI1 silabs com Smart Connected Energy friendly Rev 0 1 212 ...

Page 214: ...igure 19 10 SPI Slave Timing CKPHA 0 SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SLH T SEZ T SDZ Figure 19 11 SPI Slave Timing CKPHA 1 EFM8SB2 Reference Manual Serial Peripheral Interfaces SPI0 and SPI1 silabs com Smart Connected Energy friendly Rev 0 1 213 ...

Page 215: ...S Falling to MISO Valid 4 x TSYSCLK ns TSDZ NSS Rising to MISO High Z 4 x TSYSCLK ns TCKH SCK High Time 5 x TSYSCLK ns TCKL SCK Low Time 5 x TSYSCLK ns TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK ns TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK ns TSOH SCK Shift Edge to MISO Change 4 x TSYSCLK ns TSLH Last SCK Edge to MISO Change CKPHA 1 ONLY 6 x TSYSCLK 8 x TSYSCLK ns Note 1 TSYSCLK is equal...

Page 216: ...DLE_HIGH SCK line high in idle state 3 SLVSEL 0 R Slave Selected Flag This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave It is cleared to logic 0 when NSS is high slave not selected This bit does not indicate the instantaneous value at the NSS pin but rather a de glitched ver sion of the pin input 2 NSSIN 1 R NSS Instantaneous Pin Input This bit mimics the...

Page 217: ...ble in the receive buffer that has not been read this bit will return to logic 0 RXBMT 1 when in Master Mode In slave mode data on MOSI is sampled in the center of each data bit In master mode data on MISO is sampled one SYSCLK before the end of each data bit to provide maximum settling time for the slave device EFM8SB2 Reference Manual Serial Peripheral Interfaces SPI0 and SPI1 silabs com Smart C...

Page 218: ...s bit is valid for slave mode only and is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register If SPI interrupts are enabled an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 3 2 NSSMD 0x1 RW Slave Select Mode...

Page 219: ...SPI0CKR is the 8 bit value held in the SPI0CKR register fsck SYSCLK 2 SPI0CKR 1 for 0 SPI0CKR 255 19 4 4 SPI0DAT SPI0 Data Bit 7 6 5 4 3 2 1 0 Name SPI0DAT Access RW Reset Varies SFR Page 0x0 SFR Address 0xA3 Bit Name Reset Access Description 7 0 SPI0DAT Varies RW SPI0 Transmit and Receive Data The SPI0DAT register is used to transmit and receive SPI0 data Writing data to SPI0DAT places the data i...

Page 220: ...DLE_HIGH SCK line high in idle state 3 SLVSEL 0 R Slave Selected Flag This bit is set to logic 1 whenever the NSS pin is low indicating SPI1 is the selected slave It is cleared to logic 0 when NSS is high slave not selected This bit does not indicate the instantaneous value at the NSS pin but rather a de glitched ver sion of the pin input 2 NSSIN 1 R NSS Instantaneous Pin Input This bit mimics the...

Page 221: ...ble in the receive buffer that has not been read this bit will return to logic 0 RXBMT 1 when in Master Mode In slave mode data on MOSI is sampled in the center of each data bit In master mode data on MISO is sampled one SYSCLK before the end of each data bit to provide maximum settling time for the slave device EFM8SB2 Reference Manual Serial Peripheral Interfaces SPI0 and SPI1 silabs com Smart C...

Page 222: ...s bit is valid for slave mode only and is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI1 shift register If SPI interrupts are enabled an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 3 2 NSSMD 0x1 RW Slave Select Mode...

Page 223: ...SPI1CKR is the 8 bit value held in the SPI1CKR register fsck SYSCLK 2 SPI1CKR 1 for 0 SPI1CKR 255 19 5 4 SPI1DAT SPI1 Data Bit 7 6 5 4 3 2 1 0 Name SPI1DAT Access RW Reset Varies SFR Page 0x0 SFR Address 0x86 Bit Name Reset Access Description 7 0 SPI1DAT Varies RW SPI1 Transmit and Receive Data The SPI1DAT register is used to transmit and receive SPI1 data Writing data to SPI1DAT places the data i...

Page 224: ...es Hardware synchronization and arbitration for multi master mode Clock low extending clock stretching to interface with faster masters Hardware support for 7 bit slave and general call address recognition Firmware support for 10 bit slave address decoding Ability to inhibit all slave states Programmable data setup hold times 20 3 Functional Description 20 3 1 Supporting Documents It is assumed th...

Page 225: ...winning the arbitration It is not necessary to specify one device as the Master in a system any device who transmits a START and a slave address becomes the master for the duration of that transfer A typical SMBus transaction consists of a START condition followed by an address byte Bits7 1 7 bit slave address Bit0 R W direc tion bit one or more bytes of data and a STOP condition Bytes that are re...

Page 226: ...ow extension is used during a transfer in order to allow slower slave devices to communicate with faster masters The slave may temporarily hold the SCL line LOW to extend the clock low period effectively decreasing the serial clock frequency SCL Low Timeout If the SCL line is held low by a slave device on the bus no further communication is possible Furthermore the master cannot force the SCL line...

Page 227: ...is transferred When hardware acknowledgement is disabled the point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver When a trans mitter i e sending address data receiving an ACK this interrupt is generated after the ACK cycle so that software may read the re ceived ACK value when receiving data i e receiving address data sending an ACK...

Page 228: ...e minimum setup and hold times for the SDA line The minimum SDA setup time defines the abso lute minimum time that SDA is stable before SCL transitions from low to high The minimum SDA hold time defines the absolute mini mum time that the current SDA value remains stable after SCL transitions from high to low EXTHOLD should be set so that the mini mum setup and hold times meet the SMBus Specificat...

Page 229: ...es MASTER indicates whether a device is the master or slave during the current transfer TXMODE indicates whether the device is transmitting or receiving data for the current byte STA and STO indicate that a START and or STOP has been detected or generated since the last SMBus interrupt STA and STO are also used to generate START and STOP conditions when operating as a master Writing a 1 to STA wil...

Page 230: ... not written before the start of an SMBus frame STA A START followed by an address byte is re ceived Must be cleared by software STO A STOP is detected while addressed as a slave Arbitration is lost due to a detected STOP A pending STOP is generated ACKRQ A byte has been received and an ACK re sponse value is needed only when hard ware ACK is not enabled After each ACK cycle ARBLOST A repeated STA...

Page 231: ...recommended for applications to use hardware ACK and address recognition In some cases it may be desirable to drive ACK generation and address recognition from firmware When the EHACK bit in register SMB0ADM is cleared to 0 the firmware on the device must detect incoming slave addresses and ACK or NACK the slave address and incoming data bytes As a receiver writing the ACK bit defines the outgoing...

Page 232: ...pt serv ice routine should verify an address when it is received and clear SI as soon as possible if the address does not match to minimize clock stretching To prevent clock stretching when not being addressed enable setup and hold time extensions EXTHOLD 1 Once the hardware has matched an address and entered the interrupt service routine the firmware will not be able to use the start bit to disti...

Page 233: ...erates a STOP An SMBus inter rupt is generated at the end of all SMBus byte frames The position of the ACK interrupt when operating as a receiver depends on whether hardware ACK generation is enabled As a receiver the interrupt for an ACK occurs before the ACK with hardware ACK gener ation disabled and after the ACK when hardware ACK generation is enabled As a transmitter interrupts occur after th...

Page 234: ...wing a Master Transmitter interrupt Figure 20 5 Typical Master Write Sequence on page 233 shows a typical master write sequence as it appears on the bus and Figure 20 6 Master Write Sequence State Diagram EHACK 1 on page 234 shows the corresponding firmware state machine Two transmit data bytes are shown though any number of bytes may be transmitted Notice that all of the data byte transferred int...

Page 235: ... Yes No ACK received 1 Write next data to SMB0DAT 2 Clear the interrupt flag SI Interrupt Send Repeated Start Yes 1 Set the STO flag 2 Clear the interrupt flag SI No 1 Set the STA flag 2 Clear the interrupt flag SI Idle Interrupt b c d Figure 20 6 Master Write Sequence State Diagram EHACK 1 EFM8SB2 Reference Manual System Management Bus I2C SMB0 silabs com Smart Connected Energy friendly Rev 0 1 2...

Page 236: ...generates a NACK Software should write a 0 to the ACK bit for the last data transfer to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated The interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver Figure 20 7 Typical Master Read Se quence on page 235 shows a typical master read sequence as it ap...

Page 237: ...ag SI Send Repeated Start Yes 1 Set the STO flag 2 Clear the interrupt flag SI No 1 Set the STA flag 2 Clear the interrupt flag SI Idle Interrupt 1 Clear ACK 2 Clear SI Next Byte Final 1 Set ACK 2 Clear SI Yes No Interrupt No Yes Set the STA bit Idle b c d Figure 20 8 Master Read Sequence State Diagram EHACK 1 EFM8SB2 Reference Manual System Management Bus I2C SMB0 silabs com Smart Connected Energ...

Page 238: ...bled the SMBus hardware will automatically generate the ACK NACK and then post the interrupt It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled The interface exits Slave Receiver Mode after receiving a STOP The interface will switch to Slave Transmitter Mode if SMB0DAT is written while ...

Page 239: ... Yes No Clear SI Interrupt Clear STO Repeated Start Yes Idle No 1 Set ACK 2 Clear SI Clear SI 1 Read Data From SMB0DAT 2 Clear SI Interrupt STOP No Interrupt Yes a e b d f g c h e d h Figure 20 10 Slave State Diagram EHACK 1 EFM8SB2 Reference Manual System Management Bus I2C SMB0 silabs com Smart Connected Energy friendly Rev 0 1 238 ...

Page 240: ... After each byte is transmitted the master sends an acknowledge bit if the acknowledge bit is an ACK SMB0DAT should be writ ten with the next data byte If the acknowledge bit is a NACK SMB0DAT should not be written to before SI is cleared an error condition may be generated if SMB0DAT is written following a received NACK while in slave transmitter mode The interface exits slave trans mitter mode a...

Page 241: ...es 1 ENABLED Enable SDA extended setup and hold times 3 SMBTOE 0 RW SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low If Timer 3 is configured to Split Mode only the High Byte of the timer is held in reload while SCL is high Timer 3 should be programmed t...

Page 242: ... a start or repeated start on the bus 4 STO 0 RW SMBus Stop Flag When reading STO a 1 indicates that a stop condition was detected on the bus in slave mode or is pending in master mode When acting as a master writing a 1 to the STO bit initiates a stop condition on the bus This bit is cleared by hardware 3 ACKRQ 0 R SMBus Acknowledge Request Value Name Description 0 NOT_SET No ACK requested 1 REQU...

Page 243: ...ress 0xF4 Bit Name Reset Access Description 7 1 SLV 0x00 RW SMBus Hardware Slave Address Defines the SMBus Slave Address es for automatic hardware acknowledgement Only address bits which have a 1 in the corresponding bit position in SLVM are checked against the incoming address This allows multiple addresses to be recog nized 0 GC 0 RW General Call Address Enable When hardware address recognition ...

Page 244: ... data bytes 1 ADR_ACK_AUTOMAT IC Automatic slave address recognition and hardware acknowledge is enabled 20 4 5 SMB0DAT SMBus 0 Data Bit 7 6 5 4 3 2 1 0 Name SMB0DAT Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xC2 Bit Name Reset Access Description 7 0 SMB0DAT 0x00 RW SMBus 0 Data The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just...

Page 245: ...external oscillator clock source divided by 8 or the Comparator 1 output Timer 0 and Timer 1 may also be operated as counters When functioning as a counter a counter timer register is incremented on each high to low transition at the selected input pin T0 or T1 Events with a frequency of up to one fourth the system clock frequency can be counted The input signal need not be periodic but it must be...

Page 246: ...es1 Yes1 Notes 1 The high side overflow is used when the timer is in 16 bit mode The low side overflow is used in 8 bit mode 21 3 2 Timer 0 and Timer 1 Timer 0 and Timer 1 are each implemented as a 16 bit register accessed as two separate bytes a low byte TL0 or TL1 and a high byte TH0 or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate status T...

Page 247: ... clock cycles to ensure the level is properly sampled Clearing CT selects the clock defined by the T0M bit in register CKCON0 When T0M is set Timer 0 is clocked by the system clock When T0M is cleared Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON0 Setting the TR0 bit enables the timer when either GATE0 in the TMOD register is logic 0 or based on the input signal INT0 T...

Page 248: ...n is the same as Mode 0 except that the counter timer registers use all 16 bits The counter timers are enabled and configured in Mode 1 in the same manner as for Mode 0 The overflow rate for Timer 0 in 16 bit mode is FTIMER0 FInput Clock 216 TH0 TL0 FInput Clock 65536 TH0 TL0 EFM8SB2 Reference Manual Timers Timer0 Timer1 Timer2 and Timer3 silabs com Smart Connected Energy friendly Rev 0 1 247 ...

Page 249: ...ling the timer for the first count to be correct When in Mode 2 Timer 1 operates identically to Timer 0 The overflow rate for Timer 0 in 8 bit auto reload mode is FTIMER0 FInput Clock 28 TH0 FInput Clock 256 TH0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TR0 bit enables the timer when either GATE0 in the TMOD register is logic 0 or when the in...

Page 250: ... 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode settings To run Timer 1 while Timer 0 is in Mode 3 set the Timer 1 Mode as 0 1 or 2 To disable...

Page 251: ... 0 SYSCLK 12 To Timer 3 Low Clock Input SYSCLK T3XCLK T3ML T3MH To Timer 3 High Clock Input for split mode RTC 8 External Oscillator 8 SYSCLK 12 SYSCLK 12 Comparator 1 Figure 21 4 Timer 2 and 3 Clock Source Selection Capture Sources Capture mode allows an input to be measured against the selected clock source Timer 2 is capable of performing a capture function on the RTC clock output divided by 8 ...

Page 252: ...r interrupts are enabled an interrupt is generated on each timer overflow Additionally if the timer interrupts are enabled and the TFnLEN bit is set an interrupt is generated each time the lower 8 bits TMRnL overflow from 0xFF to 0x00 The overflow rate of the timer in split 16 bit auto reload mode is FTIMERn FInput Clock 216 TMRnRLH TMRnRLL FInput Clock 65536 TMRnRLH TMRnRLL TMRnL TMRnH Reload Int...

Page 253: ... reload mode is FTIMERn High FInput Clock 28 TMRnRLH FInput Clock 256 TMRnRLH The TFnH bit is set when TMRnH overflows from 0xFF to 0x00 the TFnL bit is set when TMRnL overflows from 0xFF to 0x00 When timer interrupts are enabled an interrupt is generated each time TMRnH overflows If timer interrupts are enabled and TFnLEN is set an interrupt is generated each time either TMRnL or TMRnH overflows ...

Page 254: ...ling edge of the input capture signal the contents of the timer register TMRnH TMRnL are loaded into the reload registers TMRnRLH TMRnRLL and the TFnH flag is set By recording the difference between two successive timer capture values the period of the captured signal can be determined with respect to the selected timer clock TMRnL TMRnH TRn TMRnRLL TMRnRLH Capture TFnCEN TFnH Interrupt Capture So...

Page 255: ...byte uses the system clock 5 T2MH 0 RW Timer 2 High Byte Clock Select Selects the clock supplied to the Timer 2 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL_CLOCK Timer 2 high byte uses the clock defined by T2XCLK in TMR2CN0 1 SYSCLK Timer 2 high byte uses the system clock 4 T2ML 0 RW Timer 2 Low Byte Clock Select Selects the clock supplied to Timer 2 If Timer 2 is confi...

Page 256: ... uses the system clock 1 0 SCA 0x0 RW Timer 0 1 Prescale These bits control the Timer 0 1 Clock Prescaler Value Name Description 0x0 SYSCLK_DIV_12 System clock divided by 12 0x1 SYSCLK_DIV_4 System clock divided by 4 0x2 SYSCLK_DIV_48 System clock divided by 48 0x3 EXTOSC_DIV_8 External oscillator divided by 8 synchronized with the system clock EFM8SB2 Reference Manual Timers Timer0 Timer1 Timer2 ...

Page 257: ...ted It can be cleared by firmware but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine in edge triggered mode 2 IT1 0 RW Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit in register IT01CF Value Name Description 0 LEVEL INT1 is level triggere...

Page 258: ... T1 5 4 T1M 0x0 RW Timer 1 Mode Select These bits select the Timer 1 operation mode Value Name Description 0x0 MODE0 Mode 0 13 bit Counter Timer 0x1 MODE1 Mode 1 16 bit Counter Timer 0x2 MODE2 Mode 2 8 bit Counter Timer with Auto Reload 0x3 MODE3 Mode 3 Timer 1 Inactive 3 GATE0 0 RW Timer 0 Gate Control Value Name Description 0 DISABLED Timer 0 enabled when TR0 1 irrespective of INT0 logic level 1...

Page 259: ...6 5 4 3 2 1 0 Name TL0 Access RW Reset 0x00 SFR Page 0x0 SFR Address 0x8A Bit Name Reset Access Description 7 0 TL0 0x00 RW Timer 0 Low Byte The TL0 register is the low byte of the 16 bit Timer 0 21 4 5 TL1 Timer 1 Low Byte Bit 7 6 5 4 3 2 1 0 Name TL1 Access RW Reset 0x00 SFR Page 0x0 SFR Address 0x8B Bit Name Reset Access Description 7 0 TL1 0x00 RW Timer 1 Low Byte The TL1 register is the low b...

Page 260: ...er is the high byte of the 16 bit Timer 0 21 4 7 TH1 Timer 1 High Byte Bit 7 6 5 4 3 2 1 0 Name TH1 Access RW Reset 0x00 SFR Page 0x0 SFR Address 0x8D Bit Name Reset Access Description 7 0 TH1 0x00 RW Timer 1 High Byte The TH1 register is the high byte of the 16 bit Timer 1 EFM8SB2 Reference Manual Timers Timer0 Timer1 Timer2 and Timer3 silabs com Smart Connected Energy friendly Rev 0 1 259 ...

Page 261: ...d input capture source and the current 16 bit timer value in TMR2H TMR2L will be cop ied to TMR2RLH TMR2RLL 3 T2SPLIT 0 RW Timer 2 Split Mode Enable When this bit is set Timer 2 operates as two 8 bit timers with auto reload Value Name Description 0 16_BIT_RELOAD Timer 2 operates in 16 bit auto reload mode 1 8_BIT_RELOAD Timer 2 operates as two 8 bit auto reload timers 2 TR2 0 RW Timer 2 Run Contro...

Page 262: ...0xCB Bit Name Reset Access Description 7 0 TMR2RLH 0x00 RW Timer 2 Reload High Byte When operating in one of the auto reload modes TMR2RLH holds the reload value for the high byte of Timer 2 TMR2H When operating in capture mode TMR2RLH is the captured value of TMR2H 21 4 11 TMR2L Timer 2 Low Byte Bit 7 6 5 4 3 2 1 0 Name TMR2L Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xCC Bit Name Reset Acces...

Page 263: ...me Reset Access Description 7 0 TMR2H 0x00 RW Timer 2 High Byte In 16 bit mode the TMR2H register contains the high byte of the 16 bit Timer 2 In 8 bit mode TMR2H contains the 8 bit high byte timer value EFM8SB2 Reference Manual Timers Timer0 Timer1 Timer2 and Timer3 silabs com Smart Connected Energy friendly Rev 0 1 262 ...

Page 264: ...ent 16 bit timer value in TMR3H TMR3L will be cop ied to TMR3RLH TMR3RLL 3 T3SPLIT 0 RW Timer 3 Split Mode Enable When this bit is set Timer 3 operates as two 8 bit timers with auto reload Value Name Description 0 16_BIT_RELOAD Timer 3 operates in 16 bit auto reload mode 1 8_BIT_RELOAD Timer 3 operates as two 8 bit auto reload timers 2 TR3 0 RW Timer 3 Run Control Timer 3 is enabled by setting thi...

Page 265: ...0x93 Bit Name Reset Access Description 7 0 TMR3RLH 0x00 RW Timer 3 Reload High Byte When operating in one of the auto reload modes TMR3RLH holds the reload value for the high byte of Timer 3 TMR3H When operating in capture mode TMR3RLH is the captured value of TMR3H 21 4 16 TMR3L Timer 3 Low Byte Bit 7 6 5 4 3 2 1 0 Name TMR3L Access RW Reset 0x00 SFR Page 0x0 SFR Address 0x94 Bit Name Reset Acces...

Page 266: ...me Reset Access Description 7 0 TMR3H 0x00 RW Timer 3 High Byte In 16 bit mode the TMR3H register contains the high byte of the 16 bit Timer 3 In 8 bit mode TMR3H contains the 8 bit high byte timer value EFM8SB2 Reference Manual Timers Timer0 Timer1 Timer2 and Timer3 silabs com Smart Connected Energy friendly Rev 0 1 265 ...

Page 267: ...ansmit is completed TI is set in SCON0 or a data byte has been received RI is set in SCON0 The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause of the UART0 interrupt transmit complete or receive complete UART0 SBUF 8 LSBs Input Shift Register RX Baud Rate Gener...

Page 268: ...uld be set so that over flows occur at twice the desired UART0 baud rate The UART0 baud rate is half of the Timer 1 overflow rate Configuring the Timer 1 overflow rate is discussed in the timer sections 22 3 2 Data Format UART0 has two options for data formatting All data transfers begin with a start bit logic low followed by the data sent LSB first and end with a stop bit logic high The data leng...

Page 269: ...T mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its ninth bit is logic 1 in a data byte the ninth bit is always set to logic 0 Setting the ...

Page 270: ...he 9th bit is logic 1 Mode 1 4 REN 0 RW Receive Enable Value Name Description 0 RECEIVE_DISABLED UART0 reception disabled 1 RECEIVE_ENABLED UART0 reception enabled 3 TB8 0 RW Ninth Transmission Bit The logic level of this bit will be sent as the ninth transmission bit in 9 bit UART Mode Mode 1 Unused in 8 bit mode Mode 0 2 RB8 0 RW Ninth Receive Bit RB8 is assigned the value of the STOP bit in Mod...

Page 271: ... two registers a transmit shift register and a receive latch register When data is written to SBUF0 it goes to the transmit shift register and is held for serial transmission Writing a byte to SBUF0 initiates the transmission A read of SBUF0 returns the contents of the receive latch EFM8SB2 Reference Manual Universal Asynchronous Receiver Transmitter 0 UART0 silabs com Smart Connected Energy frien...

Page 272: ...Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in system debugging and flash programming may be per formed C2CK is shared with the RSTb pin while the C2D signal is shared with a port I O pin This is possible because C2 communica tion is typically performed when the device is in the halt state where all on chip peripherals and user software are stalled In this h...

Page 273: ...0xB4 C2FPDAT 23 4 2 C2DEVID C2 Device ID Bit 7 6 5 4 3 2 1 0 Name C2DEVID Access R Reset 0x16 C2 Address 0x00 Bit Name Reset Access Description 7 0 C2DEVID 0x16 R Device ID This read only register returns the 8 bit device ID 0x16 EFM8SB2 23 4 3 C2REVID C2 Revision ID Bit 7 6 5 4 3 2 1 0 Name C2REVID Access R Reset Varies C2 Address 0x01 Bit Name Reset Access Description 7 0 C2REVID Varies R Revisi...

Page 274: ...ming is enabled a system reset must be issued to resume normal operation 23 4 5 C2FPDAT C2 Flash Programming Data Bit 7 6 5 4 3 2 1 0 Name C2FPDAT Access RW Reset 0x00 C2 Address 0xB4 Bit Name Reset Access Description 7 0 C2FPDAT 0x00 RW C2 Flash Programming Data Register This register is used to pass flash commands addresses and data during C2 flash accesses Valid commands are listed below 0x03 D...

Page 275: ...ter Memory Map 15 3 3 SFR Access Control Registers 20 3 3 1 SFRPAGE SFR Page 20 4 Flash Memory 21 4 1 Introduction 21 4 2 Features 23 4 3 Functional Description 24 4 3 1 Security Options 24 4 3 2 Programming the Flash Memory 25 4 3 2 1 Flash Lock and Key Functions 25 4 3 2 2 Flash Page Erase Procedure 25 4 3 2 3 Flash Byte Write Procedure 25 4 3 3 Flash Write and Erase Precautions 26 4 3 4 Minimiz...

Page 276: ... 6 2 Determining the Event that Caused the Last Wakeup 48 7 7 Power Management Control Registers 48 7 7 1 PCON0 Power Control 0 48 7 7 2 PMU0CF Power Management Unit Configuration 49 7 7 3 REG0CN Voltage Regulator Control 50 8 Clocking and Oscillators 51 8 1 Introduction 51 8 2 Features 51 8 3 Functional Description 51 8 3 1 Clock Selection 51 8 3 2 LPOSC0 20 MHz Internal Oscillator 51 8 3 3 HFOSC...

Page 277: ...Alarm Programmed Value 2 74 9 4 14 ALARM3 RTC Alarm Programmed Value 3 75 9 4 15 RTC0PIN RTC Pin Configuration 75 10 Reset Sources and Power Supply Monitor 76 10 1 Introduction 76 10 2 Features 76 10 3 Functional Description 77 10 3 1 Device Reset 77 10 3 2 Power On Reset 78 10 3 3 Supply Monitor Reset 79 10 3 4 External Reset 79 10 3 5 Missing Clock Detector Reset 79 10 3 6 Comparator CMP0 Reset ...

Page 278: ...100 12 4 1 XBR0 Port I O Crossbar 0 100 12 4 2 XBR1 Port I O Crossbar 1 102 12 4 3 XBR2 Port I O Crossbar 2 103 12 4 4 P0MASK Port 0 Mask 104 12 4 5 P0MAT Port 0 Match 105 12 4 6 P0 Port 0 Pin Latch 106 12 4 7 P0MDIN Port 0 Input Mode 107 12 4 8 P0MDOUT Port 0 Output Mode 108 12 4 9 P0SKIP Port 0 Skip 109 12 4 10 P0DRV Port 0 Drive Strength 110 12 4 11 P1MASK Port 1 Mask 111 12 4 12 P1MAT Port 1 M...

Page 279: ... 137 13 4 2 ADC0CF ADC0 Configuration 138 13 4 3 ADC0AC ADC0 Accumulator Configuration 139 13 4 4 ADC0PWR ADC0 Power Control 140 13 4 5 ADC0TK ADC0 Burst Mode Track Time 140 13 4 6 ADC0H ADC0 Data Word High Byte 140 13 4 7 ADC0L ADC0 Data Word Low Byte 141 13 4 8 ADC0GTH ADC0 Greater Than High Byte 141 13 4 9 ADC0GTL ADC0 Greater Than Low Byte 141 13 4 10 ADC0LTH ADC0 Less Than High Byte 142 13 4 ...

Page 280: ...9 16 3 2 32 bit CRC Algorithm 160 16 3 3 Writing to CRC0CN0 161 16 3 4 Using the CRC on a Data Stream 161 16 3 5 Using the CRC to Check Code Memory 161 16 3 6 Bit Reversal 161 16 4 CRC0 Control Registers 162 16 4 1 CRC0CN0 CRC0 Control 0 162 16 4 2 CRC0IN CRC0 Data Input 163 16 4 3 CRC0DAT CRC0 Data Output 163 16 4 4 CRC0AUTO CRC0 Automatic Control 163 16 4 5 CRC0CNT CRC0 Automatic Flash Sector Co...

Page 281: ...re Module Low Byte 188 17 4 17 PCA0CPH3 PCA Channel 3 Capture Module High Byte 188 17 4 18 PCA0CPM4 PCA Channel 4 Capture Compare Mode 189 17 4 19 PCA0CPL4 PCA Channel 4 Capture Module Low Byte 190 17 4 20 PCA0CPH4 PCA Channel 4 Capture Module High Byte 190 17 4 21 PCA0CPM5 PCA Channel 5 Capture Compare Mode 191 17 4 22 PCA0CPL5 PCA Channel 5 Capture Module Low Byte 192 17 4 23 PCA0CPH5 PCA Channe...

Page 282: ...figuring the SMBus Module 226 20 3 4 Hardware ACK Multimaster and Multislave Behavior 231 20 3 5 Operational Modes 232 20 4 SMB0 Control Registers 240 20 4 1 SMB0CF SMBus 0 Configuration 240 20 4 2 SMB0CN0 SMBus 0 Control 241 20 4 3 SMB0ADR SMBus 0 Slave Address 242 20 4 4 SMB0ADM SMBus 0 Slave Address Mask 243 20 4 5 SMB0DAT SMBus 0 Data 243 21 Timers Timer0 Timer1 Timer2 and Timer3 244 21 1 Intr...

Page 283: ...ersal Asynchronous Receiver Transmitter 0 UART0 266 22 1 Introduction 266 22 2 Features 266 22 3 Functional Description 267 22 3 1 Baud Rate Generation 267 22 3 2 Data Format 267 22 3 3 Data Transfer 268 22 3 4 Multiprocessor Communications 268 22 4 UART0 Control Registers 269 22 4 1 SCON0 UART0 Serial Port Control 269 22 4 2 SBUF0 UART0 Serial Port Data Buffer 270 23 C2 Debug and Programming Inte...

Page 284: ...lth which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons Trade...

Page 285: ...ion Silicon Laboratories EFM8SB20F32G A QFN24 EFM8SB20F64G A QFP32 EFM8SB20F16G A QFN24 EFM8SB20F32G A QFP32 EFM8SB20F64G A QFN24 EFM8SB20F64G A QFN32 EFM8SB20F32G A QFN32 EFM8SB20F64G A QFN24R EFM8SB20F32G A QFN32R EFM8SB20F16G A QFN24R EFM8SB20F64G A QFP32R EFM8SB20F32G A QFN24R EFM8SB20F32G A QFP32R ...

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