REMOTE CONTROL
181
Bit Definition for the Status Byte Register
Bit number
Decimal Value Definition
0 Not used
1
Not used, returns “0”
1 Not used
2
Not used, returns “0”
2 Error Queue
4
Indicates that one or more errors are
stored in the error queue.
3 Questionable
Summary bit
8
One or more bits are set in the
questionable data register (for
enabled events).
4 Message
Available bit
16
Indicates that a message is available
in the output queue.
5 Stardard Event
Summary bit
32
Indicates that one or more bits are
set in the standard event register.
(For enabled events).
6 Master
Summary bit
64
Indicates that a summary bit is set in
the status byte register. (for enabled
summary bits)
7 Unused
128
Not used, returns “0”
The status byte condition register is cleared when one of the
following occurs:
*CLS command is used to clear the status byte
register.
You read the event register from another
register group (only clear the corresponding bit
in the condition register)
The status byte enable register is cleared when the following occurs:
When the *SRE 0 is command is executed.
Use the *STB? query to read the status byte register.
The *STB? query will return the contents of the status byte register
as long as the bit 6 (MSS) has been cleared.
Using the *OPC? query to place a signal in the output buffer.
Summary of Contents for T3PS13206P
Page 1: ... ...
Page 106: ...T3PSX3200P Series User Manual 106 Register Commands OPC 187 OPC 187 ...
Page 177: ...REMOTE CONTROL 177 Example SAV 1 Recalls the setting stored in memory 2 STATE02 ...
Page 185: ...REMOTE CONTROL 185 Example STB Returns 81 if the status byte register is set to 0101 0001 ...
Page 196: ...T3PSX3200P Series User Manual 196 Between chassis and DC power cord 30MΩ or above DC 500V ...
Page 197: ... 0 0 0 1 2 3 4 5 6 7 8 8 9 3 3 3 45 6 990 0 0 9 0 0 0 9 0 0 0 0 9 7 7 88 8 1 931711 RevB ...