ADV8005 Hardware Reference Manual
UG-707
pvsp_dp_4kx2k_mode_en
, Primary VSP Map,
Address 0xE869[4]
This bit is used to make the VOM display module work in 4K x 2K mode. This register's value will be used while pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_4kx2k_mode_en
Description
0 (default)
Not in 4K x 2K mode
1
In 4K x 2K mode
pvsp_data_clipping_en
, Primary VSP Map,
Address 0xE84E[3]
This bit is used to limit the output data within range of 16~235.
Function
pvsp_data_clipping_en
Description
0 (default)
Not limit output data.
1
Limit output data
pvsp_man_dp_timing_enable
, Primary VSP Map,
Address 0xE883[0]
This bit is used to enable the manual setting of the display port's timing.
Function
pvsp_man_dp_timing_enabl
e
Description
0 (default)
Disable manually setting output timing
1
Enable manually setting output timing
pvsp_dp_decount[12:0]
, Primary VSP Map,
Address 0xE856[4:0]; Address 0xE857[7:0]
This signal is used to set the DE duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_decount[12:0]
Description
0x000 (default)
Default
0xXXX
Data enable count of output timing
pvsp_dp_hfrontporch[11:0]
, Primary VSP Map,
Address 0xE858[3:0]; Address 0xE859[7:0]
This signal is used to set the horizontal front porch duration of output timing. This register's value will be used while
pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_hfrontporch[11:0]
Description
0x000 (default)
Default
0xXXX
Horizontal front porch of output timing
pvsp_dp_hsynctime[11:0]
, Primary VSP Map,
Address 0xE85A[3:0]; Address 0xE85B[7:0]
This signal sets the Hsync duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_hsynctime[11:0]
Description
0x000 (default)
Default
0xXXX
Hsync width of output timing
pvsp_dp_hbackporch[11:0]
, Primary VSP Map,
Address 0xE85C[3:0]; Address 0xE85D[7:0]
This signal is used to set the horizontal back porch duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_hbackporch[11:0]
Description
0x000 (default)
Default
0xXXX
Horizontal back porch of output timing
pvsp_dp_activeline[11:0]
, Primary VSP Map,
Address 0xE85E[3:0]; Address 0xE85F[7:0]
This signal is used to set the active line number of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.
Function
pvsp_dp_activeline[11:0]
Description
0x000 (default)
Default
0xXXX
Active lines of output timing
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