ADV8005 Hardware Reference Manual
UG-707
Table 51: HDMI Tx Interrupt Bits in Main Map Register 0xEC97
Bit Name
Bit Position
Description
bksv_flag_int
6
When set to 1 it indicates that the KSVs from the downstream sink have been read and available in the
Memory Map. Once set, it remains high until it is cleared by setting it to 1.
hdcp_error_int
7
When set to 1 it indicates that the HDCP/EDID controller has reported an error. This error is available in
HDCP_CONTROLLER_ERROR. Once set, it remains high until it is cleared by setting it to 1.
Table 52: Status Bits in Main Map Register 0xEC42
Bit Name
Bit Position
Description
hpd_state
6
See description for
rx_sense_state
5
See description for
6.7.2.
VSYNC Interrupt
The time taken for the VSYNC interrupt to trigger depends on the processing done internally, such as 422 to 444 conversion or CSC adjustments.
The table below details the typical time taken for VSYNC interrupts to trigger after the VSYNC has been received at the TTL input. For these
measurements, the video was routed routed from the TTL input directly to the TX and not routed through the VSP. If the data is routed through
the 422 to 444 block, an extra delay of 2 pixel clock cycles can be expected. If the CSC block is also included, an additional delay of 9 clock
periods can be expected.
Table 53 Typical times for VSYNC interrupt to Trigger using the TTL digital input Port
Video Format
Pixel Clock Frequency
Typical VSYNC Interrupt Delay
4K2K30
148 MHz
2 µs
1080P60
148 MHz
2 µs
480P60
27 MHz
4 µs
480i60
13.5 MHz
5 µs
6.8.
EDID/HDCP CONTROLLER STATUS
The Tx core features an EDID/HDCP controller which handles EDID extraction from the downstream sink. This EDID/HDCP controller also
handles HDCP authentication with downstream sink. The tasks that the Tx EDID/HDCP controller performs are described in Section
and
Section
The current state of the Tx EDID/HDCP controller can be read from the
hdcp_controller_state[3:0]
, TX2 Main Map,
Address 0xF4C8[3:0] (Read Only)
This signal is used to readback the state of the EDID/HDCP controller.
Function
hdcp_controller_state[3:0]
Description
0000 (default)
In Reset (No Hot Plug Detected)
0001
Reading EDID
0010
In Idle state (Waiting for HDCP Request)
0011
Initializing HDCP
0100
HDCP enabled
0101
Initializing HDCP Repeater
0110 - 1111
Reserved
6.9.
EDID/HDCP CONTROLLER ERROR CODES
If an HDCP authentication occurs between the
and the downstream sink, the
can trigger an interrupt to notify this error
to the user or the controlling CPU. The EDID/HDCP controller will then report the HDCP error code via the status field
. The error code is only valid when the
hdcp_error_int
interrupt bit is set to 1. The last error code will remain in the
HDCP/EDID controller error field even when the interrupt is cleared.
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