ADV8005 Hardware Reference Manual
UG-707
exosd_ddr_edge_sel
, IO Map,
Address 0x1B6A[3]
This bit is used to select which edge the first sample of DDR data is latched on.
Function
exosd_ddr_edge_sel
Description
0 (default)
Posedge data first
1
Negedge data first
Using the pixel clock as a reference,
expects the Y sample on a rising edge and then a chroma sample on the falling edge. When
expects a chroma sample on the rising edge and the Y sample on the falling edge.
can be used to swap the order of the chroma data. By default,
expects a sequence of Cb, Cr, Cb, Cr… When
is set,
expects a sequence of Cr, Cb, Cr, Cb....
exosd_swap_cb_cr_422
, IO Map,
Address 0x1B69[7]
This bit is used to swap the order of the C data when decoding 4:2:2 data.
Function
exosd_swap_cb_cr_422
Description
0 (default)
Cb/Cr decoding
1
Cr/Cb decoding
is used to convert from pseudo 444 video data to real 444. All processing occurs in the
Therefore, if video input to the device is not in this format, it must be first converted to 4:4:4. Setting this bit to 1 converts video data to 4:4:4.
exosd_ps444_r444_conv
, IO Map,
Address 0x1B69[6]
This bit is used to convert 4:2:2 data to pseudo 444 or to real 444.
Function
exosd_ps444_r444_conv
Description
0 (default)
Nothing done.
1
Pseudo444 to Real 444 conversion.
is used to reverse the order of the video TTL input. By default, this is set to non reversed.
exosd_rev_bus
, IO Map,
Address 0x1B6B[4]
This bit is used to reverse the input video bus, i.e. D[23:0] -> D[0:23].
Function
exosd_rev_bus
Description
0 (default)
Reverse the pin mapping on the OSD bus
1
Use the OSD bus as it comes from the pins
configure the polarity of the input video timing signals. These must be set depending on the
polarity of the upstream IC. If active low, these register can be left at their default. If these signals from the upstream IC are active high, their
polarity can be inverted.
exosd_hs_pol
, IO Map,
Address 0x1B69[0]
This bit is used to set the polarity of the input External OSD HS timing signal.
Function
exosd_hs_pol
Description
0 (default)
Input HS polarity doesn’t change.
1
Input HS polarity gets inverted.
exosd_vs_pol
, IO Map,
Address 0x1B69[1]
This bit is used to set the polarity of the input External OSD VS timing signal.
Function
exosd_vs_pol
Description
0 (default)
Input VS polarity doesn’t change.
1
Input VS polarity gets inverted.
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