UG-707
ADV8005 Hardware Reference Manual
6.13.3.
Software Implementation
shows a block diagram of HDCP software implementation for all cases using the
Tx HDCP/EDID controller state machine.
The necessary interactions with the
registers and EDID memory, as well as when these interactions should take place, are illustrated
in the diagram. Note that there is no need to interact with the DDC bus directly because all of the DDC functionality is controlled by the Tx
HDCP/EDID controller and follows the
HDCP specification 1.4.
START
Wait For BKSV
ready interrupt
Set HDCP
Request Bit
HDCP_DESIRED
to 1
Is Sink
Repeater?
BCAPS[5]
==1
NO
Wait for Controller
State == 4
HDCP_CONTROLL
ER_STATE
Check Number of
BKSVs available
BKSV_COUNT
Wait For BKSV
ready interrupt or
Controller State = 4
HDCP_CONTROLL
ER_STATE
Controller
State == 4?
Compare BKSVs
with Revocation
List
Send Audio and
Video Across
HDMI Link
YES
NO
If HDMI Tx is part
of a repeater
store BSTATUS
info from EDID
memory 1
st
time
this state is
reached
If HDMI Tx is part
of a repeater
send DEPTH and
DEVICE_COUNT
to receiver
Wait 2 Seconds
HDCP Link
OK?
ENCRYPTIO
N_ON == 1
Clear HDCP
Request, return
to START
YES
YES
Compare BKSVs
with Revocation
List
Read BKSVs
From Registers
Tx EDID map
Clear BKSV Ready
Flag. Set
BKSV_FLAG_INT to
1
Read BKSVs
from EDID
memeroy
Clear BKSV Ready
Flag. Set
BKSV_FLAG_INT to
1
Figure 108: HDCP Software Implementation
Rev. A | Page 238 of 317
