UG-707
ADV8005 Hardware Reference Manual
if video input to the device is not in this format, this must be first converted to 4:4:4. Setting this bit to 1 converts video data to 4:4:4.
vid_ps444_r444_conv
, IO Map,
Address 0x1B49[6]
This bit is used to convert 4:2:2 data to pseudo 444 or to real 444.
Function
vid_ps444_r444_conv
Description
0 (default)
Nothing done
1
Pseudo 444 to Real 444 conversion
and
configure the polarity of the input video timing signals. These must be set depending on
the polarity of the upstream IC. If active low, these register can be left at their default. If these signals from the upstream IC are active high, their
polarity can be inverted.
vid_hs_pol
, IO Map,
Address 0x1B49[3]
This bit is used to set the polarity of the input HS timing signal.
Function
vid_hs_pol
Description
0 (default)
Input HS polarity does not change
1
Input HS polarity gets inverted
vid_vs_pol
, IO Map,
Address 0x1B49[2]
This bit is used to set the polarity of the input VS timing signal.
Function
vid_vs_pol
Description
0 (default)
Input VS polarity does not change
1
Input VS polarity gets inverted
vid_de_pol
, IO Map,
Address 0x1B49[1]
This bit is used to set the polarity of the input DE enable signal.
Function
vid_de_pol
Description
0 (default)
Input DE polarity does not change
1
Input DE polarity gets inverted
vid_fld_pol
, IO Map,
Address 0x1B49[0]
This bit is used to set the polarity of the input Field (FLD) timing signal.
Function
vid_fld_pol
Description
0 (default)
Input FLD polarity does not change
1
Input FLD polarity gets inverted
is used to select the method by which the input video will be synchronized. This may be required when the
in conjunction with an MPEG decoder. MPEG decoders use embedded timing codes rather than using external HS and VS signals. Similarly,
other ADI decoders/HDMI Rxs can output video using embedded timing codes. This register should be programmed depending on the timing
method of the upstream IC.
Refer to Section
for more information on AV-codes.
vid_hs_vs_mode
, IO Map,
Address 0x1B4B[7]
This bit is used to select the method of input timing.
Function
vid_hs_vs_mode
Description
0
Use embedded SAV/EAV codes
1 (default)
Use external HS/VS synchronization signals
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