UG-707
ADV8005 Hardware Reference Manual
pvsp_vin_h[10:0]
, Primary VSP Map,
Address 0xE82E[2:0]; Address 0xE82F[7:0]
This signal is used to set the horizontal resolution of the input video. This register's value will be used while pvsp_man_input_res is 1 or
pvsp_autocfg_input_vid is 0.
Function
pvsp_vin_h[10:0]
Description
0x000 (default)
Default
0xXXX
Horizontal resolution of input video
pvsp_vin_v[10:0]
, Primary VSP Map,
Address 0xE830[2:0]; Address 0xE831[7:0]
This signal is used to set the vertical resolution of the input video. This register's value will be used while pvsp_man_input_res is 1 or
pvsp_autocfg_input_vid is 0.
Function
pvsp_vin_v[10:0]
Description
0x000 (default)
Default
0xXXX
Vertical resolution of input video
Similarly, if the output timing is not in the PVSP output format table, customized output format needs to be set manually. The detailed
configuration instructions are given in the PVSP VOM output port description.
3.2.1.3.
Field/Frame Buffer Number
Depending on the type of conversion that is to take place, a number of buffers must be allocated for the input/output video data. Depending on
the conversion required, this should be set in the
.
can be automatically set by
and
register does not change when crop or album mode
is enabled.
pvsp_fieldbuf_num[2:0]
, Primary VSP Map,
Address 0xE829[2:0]
Sets the number of field/frame buffers.
Function
pvsp_fieldbuf_num[2:0]
Description
000
Default
XXX
Number of field/frame buffers
3.2.1.4.
Field/Frame Buffer Address and Size
In order to store video data in external memory in the correct size fields, the buffer size of the external DDR2 memory must be programmed
by the user. Configuring this manually allows the user to have very flexible control over the external DDR memory.
These programmed field buffers or frame buffers are allocated by setting the following registers:
pvsp_fieldbuffer1_addr[31:0]
pvsp_fieldbuffer2_addr[31
Rev. A | Page 108 of 317
