Rev. 1.10
78
November 26, 2019
Rev. 1.10
79
November 26, 2019
HT68FB240
USB Low Speed Flash MCU
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I
2
C
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I
2
C flags
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
Bit 0
Unimplemented, read as "0"
SIMC2 Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
CKPOLB
CKEG
MLS
CSEN
WCOL
TRF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
D7, D6:
Undefined bit
This bit can be read or written by user software program.
Bit 5
CKPOLB:
Determines the base condition of the clock line
0: the SCK line will be high when the clock is inactive
1: the SCK line will be low when the clock is inactive
The CKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCK line will be low when the clock is inactive. When the CKPOLB bit is
low, then the SCK line will be high when the clock is inactive.
Bit 4
CKEG:
Determines SPI SCK active clock edge type
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs
and inputs data on the SPI bus. These two bits must be configured before data transfer
is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit
determines the base condition of the clock line, if the bit is high, then the SCK line
will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK
line will be high when the clock is inactive. The CKEG bit determines active clock
edge type which depends upon the condition of CKPOLB bit.
Bit 3
MLS:
SPI Data shift order
0: LSB
1: MSB
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
Bit 2
CSEN:
SPI
SCS pin Control
0: Disable
1: Enable
The CSEN bit is used as an enable/disable for the
SCS
pin. If this bit is low, then the
SCS
pin will be disabled and placed into a floating condition. If the bit is high the
SCS
pin will be enabled and used as a select pin.
Note that using the CSEN bit can be disabled or enabled via configuration option.
Bit 1
WCOL:
SPI Write Collision flag
0: No collision
1: Collision
The WCOL flag is used to detect if a data collision has occurred. If this bit is high it
means that data has been attempted to be written to the SIMD register during a data
transfer operation. This writing operation will be ignored if data is being transferred.
The bit can be cleared by the application program. Note that using the WCOL bit can
be disabled or enabled via configuration option.
