XC2200 Derivatives
System Units (Vol. 1 of 2)
Architectural Overview
User’s Manual
2-8
V2.1, 2008-08
ArchitectureX22, V1.1
2.1.5
Programmable Multiple Priority Interrupt System
The XC2200 provides 96 separate interrupt nodes that may be assigned to 16 priority
levels with 8 group priorities on each level. Most interrupt sources are connected to a
dedicated interrupt node. In some cases, multi-source interrupt nodes are incorporated
for efficient use of system resources. These nodes can be activated by several source
requests and are controlled via interrupt subnode control registers.
The following enhancements within the XC2200 allow processing of a large number of
interrupt sources:
• Peripheral Event Controller (PEC): This processor is used to off-load many interrupt
requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap
routines by performing single-cycle interrupt-driven byte or word data transfers
between any two locations with an optional increment of the PEC source pointer, the
destination pointer, or both. Only one cycle is ‘stolen’ from the current CPU activity to
perform a PEC service.
• Multiple Priority Interrupt Controller: This controller allows all interrupts to be assigned
any specified priority. Interrupts may also be grouped, which enables the user to
prevent similar priority tasks from interrupting each other. For each of the interrupt
nodes, there is a separate control register which contains an interrupt request flag, an
interrupt enable flag, and an interrupt priority bitfield. After being accepted by the CPU,
an interrupt service can be interrupted only by a higher prioritized service request. For
standard interrupt processing, each of the interrupt nodes has a dedicated vector
location.
• Multiple Register Banks: Two local register banks for immediate context switching add
to a relocatable global register bank. The user can specify several register banks
located anywhere in the internal DPRAM and made of up to sixteen general purpose
registers. A single instruction switches from one register bank to another (switching
banks flushes the pipeline, changing the global bank requires a validation sequence).
The XC2200 is capable of reacting very quickly to non-deterministic events because its
interrupt response time is within a very narrow range of typically 7 clock cycles (in the
case of internal program execution). Its fast external interrupt inputs are sampled every
clock cycle and allow even very short external signals to be recognized.
The XC2200 also provides an excellent mechanism to identify and process exceptions
or error conditions that arise during run-time, so called ‘Hardware Traps’. A hardware
trap causes an immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Unless another, higher prioritized, trap service is in progress, a hardware trap will
interrupt any current program execution. In turn, a hardware trap service can normally
not be interrupted by a standard or PEC interrupt.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
