CHAPTER 15 SERIAL INTERFACE IICA
Page 445 of 920
15.3.6
IICA low-level width setting register n (IICWLn)
This register is used to set the low-level width (t
LOW
) of the SCLAn pin signal that is output by serial interface
IICA and to control the SDAAn pin signal.
The data hold time is decided by value the higher 6 bits of IICWL register.
The IICWLn register can be set by an 8-bit memory manipulation instruction.
Set the IICWLn register while operation of I
2
C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is
0).
Reset signal generation sets this register to FFH.
For details about setting the IICWLn register, see
15.4.2 Setting transfer clock by using IICWLn and IICWHn
The data hold time is a quarter of the time specified by IICWLn.
Figure 15 - 16 Format of IICA low-level width setting register n (IICWLn)
15.3.7
IICA high-level width setting register n (IICWHn)
This register is used to set the high-level width of the SCLAn pin signal that is output by serial interface IICA and
to control the SDAAn pin signal.
The IICWHn register can be set by an 8-bit memory manipulation instruction.
Set the IICWHn register while operation of I
2
C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is
0).
Reset signal generation sets this register to FFH.
Figure 15 - 17 Format of IICA high-level width setting register n (IICWHn)
Remark 1.
For setting procedures of the transfer clock on master side and of the IICWLn and IICWHn registers on slave
side, see
and
, respectively.
Remark 2.
n = 0, 1
Address: F0232H (IICWL0), F023AH (IICWL1)
After reset: FFH
Symbol
7
6
5
4
3
2
1
0
IICWLn
Address: F0233H (IICWH0), F023BH (IICWH1)
After reset: FFH
Symbol
7
6
5
4
3
2
1
0
IICWHn
Summary of Contents for RL78/G1H
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