CHAPTER 6 CLOCK GENERATOR
Page 137 of 920
6.6.6
Time required for switchover of CPU clock and main system clock
By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched
(between the main system clock and the subsystem clock), and main system clock can be switched (between the
high-speed on-chip oscillator clock and the high-speed system clock).
The actual switchover operation is not performed immediately after rewriting to the CKC register; operation
continues on the pre-switchover clock for several clocks (see
to
).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7
(CLS) of the CKC register. Whether the main system clock is operating on the high-speed system clock or high-
speed on-chip oscillator clock can be ascertained using bit 5 (MCS) of the CKC register.
When the CPU clock is switched, the peripheral hardware clock is also switched.
Remark 1.
The number of clocks listed in Tables 6 - 11 and 6 - 12 is the number of CPU clocks before switchover.
Remark 2.
Calculate the number of clocks in Tables 6 - 11 and 6 - 12 by rounding up the number after the decimal position.
Example
When switching the main system clock from the high-speed system clock to the high-speed on-chip oscillator
clock (@ oscillation with f
IH
= 8 MHz, f
MX
= 10 MHz)
2 f
MX
/f
IH
= 2 (10/8) = 2.5
→
3 clocks
Table 6 - 10 Maximum Time Required for Main System Clock Switchover
Clock A
Switching directions
Clock B
Remark
f
IH
f
MX
f
MAIN
f
SUB
Table 6 - 11 Maximum Number of Clocks Required for f
IH
↔
f
MX
Set Value Before Switchover
Set Value After Switchover
MCM0
MCM0
0
(f
MAIN
= f
IH
)
1
(f
MAIN
= f
MX
)
0
(f
MAIN
= f
IH
)
f
MX
≥
f
IH
2 clock
f
MX
<
f
IH
2 f
IH
/f
MX
clock
1
(f
MAIN
= f
IH
)
f
MX
≥
f
IH
2 f
MX
/f
IH
clock
f
MX
<
f
IH
2 clock
Table 6 - 12 Maximum Number of Clocks Required for f
MAIN
↔
f
SUB
Set Value Before Switchover
Set Value After Switchover
CSS
CSS
0
(f
CLK
= f
MAIN
)
1
(f
CLK
= f
SUB
)
0
(f
CLK
= f
MAIN
)
1 + 2 f
MAIN
/f
SUB
clock
1
(f
CLK
= f
SUB
)
3 clock
Summary of Contents for RL78/G1H
Page 941: ...R01UH0575EJ0120 RL78 G1H...
