MC96F6432
126
June 22, 2018 Ver. 2.9
11.5.4 8-Bit Capture Mode
The timer 0 capture mode is set by T0MS[1:0]
as ‘1x’. The clock source can use the internal/external clock.
Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T0CNT is equal
to T0DR. T0CNT value is automatically cleared by match signal and it can be also cleared by software (T0CC).
This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the
maximum period of timer.
The capture result is loaded into T0CDR. In the timer 0 capture mode, timer 0 output (T0O) waveform is not
available.
According to EIPOL1 registers setting, the external interrupt EINT10 function is chosen. Of course, the EINT10
pin must be set to an input port.
T0CDR and T0DR are in the same address. In the capture mode, reading operation reads T0CDR, not T0DR
and writing operation will update T0DR.
P
r
e
s
c
a
l
e
r
fx
M
U
X
fx/2
T0CNT(8Bit)
EC0
fx/4
fx/8
fx/32
fx/128
fx/512
fx/2048
3
T0CK[2:0]
T0EN
8-bit Timer 0 Counter
T0DR(8Bit)
Comparator
T0IFR
8-bit Timer 0 Data Register
INT_ACK
Clear
Match
MUX
T0CDR(8Bit)
Clear
FLAG10
(EIFLAG1.0)
2
T0MS[1:0]
2
T0MS[1:0]
INT_ACK
Clear
To interrupt
block
To interrupt
block
T0EN
-
T0MS1
T0MS0
T0CK2
T0CK1
T0CK0
T0CC
T0CR
1
-
1
x
x
x
x
x
ADDRESS : B2H
INITIAL VALUE: 0000_0000B
Clear
EINT10
EIPOL1[1:0]
2
Match signal
T0CC
Figure 11.10 8-Bit Capture Mode for Timer 0
Summary of Contents for MC96F6432 Series
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
