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ARM Cortex-A53 MPCore, Technical Reference Manual

The ARM Cortex-A53 MPCore is a powerful multicore processor combining optimum performance and energy efficiency. Utilize its full potential by easily accessing the comprehensive Technical Reference Manual, available for free download at 88.208.23.73:8080. Get detailed insights and unleash the capabilities of this exceptional product.

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Level 1 Memory System 

ARM DDI 0500D

Copyright © 2013-2014 ARM. All rights reserved.

6-3

ID021414

Non-Confidential

6.2

Cache behavior

You cannot disable the L2 and L1 Data caches independently, because they are controlled by the 
same enable. See 

System Control Register

 on page 4-191

. On a cache miss, critical word-first 

filling of the cache is performed.

If the cache reports a hit on a memory location that is marked as Non-Cacheable or Device, this 
is called an unexpected cache hit. In this architecturally 

UNPREDICTABLE

 case, the cache might 

return incorrect data. Because the caches are physically addressed, improper translation table 
configuration can create this scenario. Disabling the cache can also create this situation. 
Non-Cacheable or Device accesses do not lookup in the cache, and therefore ignore any 
unexpected cache hit.

6.2.1

Instruction cache disabled behavior

If the instruction cache is disabled, fetches cannot access any of the instruction cache arrays. An 
exception to this rule is the CP15 instruction cache operations. If the instruction cache is 
disabled, the instruction cache maintenance operations can still execute normally.

If the instruction cache is disabled, all instruction fetches to cacheable memory are treated as if 
they were non-cacheable. This means that instruction fetches might not be coherent with caches 
in other cores, and software must take account of this.

6.2.2

Instruction cache speculative memory accesses

Because there can be several unresolved branches in the pipeline, instruction fetches are 
speculative, meaning there is no guarantee that they are executed. A branch or exceptional 
instruction in the code stream can cause a pipeline flush, discarding the currently fetched 
instructions. Because of the aggressive prefetching behavior, you must not place read-sensitive 
devices in the same page as code. Pages with Device memory type attributes are treated as 
Non-Cacheable Normal Memory. You must mark pages that contain read-sensitive devices with 
the translation table descriptor XN (Execute Never) attribute bit. To avoid speculative fetches 
to read-sensitive devices when address translation is disabled, these devices and code that are 
fetched must be separated in the physical memory map. See the 

ARM

®

 Architecture Reference 

Manual ARMv8, for ARMv8-A architecture profile 

for more information.

6.2.3

Data cache disabled behavior

If the data cache is disabled, loads and store instructions do not access any of the L2 or L1 Data 
cache arrays. An exception to this rule is the CP15 data cache operations. If the data cache is 
disabled, the data cache maintenance operations can still execute normally.

If the data cache is disabled, all loads and store instructions to cacheable memory are treated as 
if they were non-cacheable. This means that they are not coherent with the caches in this core 
or the caches in other cores, and software must take account of this.

6.2.4

Data cache maintenance considerations

DCIMVAC operations in AArch32 and DC IVAC instructions in AArch64 perform an 
invalidate of the target address. If the data is dirty in the executing core then a clean is performed 
before the invalidate.

DCISW operations in AArch32 and DC ISW instructions in AArch64 perform both a clean and 
invalidate of the target set/way. The values of HCR.SWIO and HCR_EL2.SWIO have no effect.

Summary of Contents for Cortex-A53 MPCore

Page 1: ...Copyright 2013 2014 ARM All rights reserved ARM DDI 0500D ID021414 ARM Cortex A53 MPCore Processor Revision r0p2 Technical Reference Manual ...

Page 2: ... in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any inco...

Page 3: ... 3 1 3 Features 1 5 1 4 Interfaces 1 6 1 5 Implementation options 1 7 1 6 Test features 1 9 1 7 Product documentation and design flow 1 10 1 8 Product revisions 1 12 Chapter 2 Functional Description 2 1 About the Cortex A53 processor functions 2 2 2 2 Interfaces 2 7 2 3 Clocking and resets 2 9 2 4 Power management 2 16 Chapter 3 Programmers Model 3 1 About the programmers model 3 2 3 2 ARMv8 A arc...

Page 4: ...interface 7 13 7 5 Additional memory attributes 7 17 7 6 Optional integrated L2 cache 7 18 7 7 ACP 7 19 Chapter 8 Cache Protection 8 1 Cache protection behavior 8 2 8 2 Error reporting 8 4 Chapter 9 Generic Interrupt Controller CPU Interface 9 1 About the GIC CPU Interface 9 2 9 2 GIC programmers model 9 3 Chapter 10 Generic Timer 10 1 About the Generic Timer 10 2 10 2 Generic Timer functional des...

Page 5: ... 14 2 Trigger inputs and outputs 14 3 14 3 Cortex A53 CTM 14 4 14 4 Cross trigger register summary 14 5 14 5 Cross trigger register descriptions 14 8 Appendix A Signal Descriptions A 1 About the signal descriptions A 2 A 2 Clock signals A 3 A 3 Reset signals A 4 A 4 Configuration signals A 5 A 5 Generic Interrupt Controller signals A 6 A 6 Generic Timer signals A 8 A 7 Power management signals A 9...

Page 6: ...14 ARM All rights reserved vi ID021414 Non Confidential Preface This preface introduces the ARM Cortex A53 MPCore Processor Technical Reference Manual It contains the following sections About this book on page vii Feedback on page xi ...

Page 7: ...troduction Read this for an introduction to the Cortex A53 processor and descriptions of the major features Chapter 2 Functional Description Read this for a description of the functionality of the Cortex A53 processor Chapter 3 Programmers Model Read this for a description of the programmers model Chapter 4 System Control Read this for a description of the system registers and programming informat...

Page 8: ...s for a description of the technical changes between released issues of this book Glossary The ARM Glossary is a list of terms used in ARM documentation together with definitions for those terms The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning See ARM Glossary http infocenter arm com help topic com arm doc aeg0014...

Page 9: ...otes an active LOW signal Additional reading This section lists publications by ARM and by third parties See Infocenter http infocenter arm com for access to ARM documentation monospace Denotes a permitted abbreviation for a command or option You can enter the underlined text instead of the full command or option name monospace italic Denotes arguments to monospace text where the argument is to be...

Page 10: ... ADIv5 0 to ADIv5 2 ARM IHI 0031 ARM AMBA 4 ATB Protocol Specification ARM IHI 0032 ARM Generic Interrupt Controller Architecture Specification ARM IHI 0048 ARM ETM Architecture Specification ETMv4 ARM IHI 0064 The following confidential books are only available to licensees ARM Cortex A53 MPCore Processor Cryptography Extension Technical Reference Manual ARM DDI 0501 ARM Cortex A53 MPCore Process...

Page 11: ...ith as much information as you can provide Include symptoms and diagnostic procedures if appropriate Feedback on content If you have comments on content then send an e mail to errata arm com Give The title The number ARM DDI 0500D The page numbers to which your comments apply A concise explanation of your comments ARM also welcomes general suggestions for additions and improvements Note ARM tests ...

Page 12: ...ces the Cortex A53 processor and its features It contains the following sections About the Cortex A53 processor on page 1 2 Compliance on page 1 3 Features on page 1 5 Interfaces on page 1 6 Implementation options on page 1 7 Test features on page 1 9 Product documentation and design flow on page 1 10 Product revisions on page 1 12 ...

Page 13: ...ple of a Cortex A53 MPCore configuration with four cores and either an ACE or a CHI interface Figure 1 1 Example Cortex A53 processor configuration See About the Cortex A53 processor functions on page 2 2 for more information about the functional components Core 3 Core 2 Core 1 AXI slave interface Core 0 Timer events Counter ICDT nIRQ nFIQ PMU ATB Debug Core Trace Debug Interrupt Timer ACP Power m...

Page 14: ...viously called the Thumb instruction set The A64 instruction set The Cortex A53 processor supports the following architecture extensions Optional Advanced SIMD and Floating point Extension for integer and floating point vector operations Note The Advanced SIMD architecture its associated implementations and supporting software are commonly referred to as NEON technology To perform floating point o...

Page 15: ...ure See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile 1 2 5 Debug architecture The Cortex A53 processor implements the ARMv8 Debug architecture The CoreSight Cross Trigger Interface CTI enables the debug logic the Embedded Trace Macrocell ETM and the Performance Monitor Unit PMU to interact with each other and with other CoreSight components For more information see ...

Page 16: ...eatures Full implementation of the ARMv8 A architecture instruction set with the architecture options listed in ARM architecture on page 1 3 In order pipeline with symmetric dual issue of most instructions Harvard Level 1 L1 memory system with a Memory Management Unit MMU Level 2 L2 memory system providing cluster memory coherency optionally including an L2 cache ...

Page 17: ...ce that implements either an ACE or CHI interface Optional Accelerator Coherency Port ACP that implements an AXI slave interface Debug interface that implements an APB slave interface Trace interface that implements an ATB interface CTI Design for Test DFT Memory Built In Self Test MBIST Q channel for power management See Interfaces on page 2 7 for more information on each of these interfaces ...

Page 18: ...ores Up to four cores L1 Instruction cache size 8K 16K 32K 64K L1 Data cache size 8K 16K 32K 64K L2 cache Included or not L2 cache size 128K 256K 512K 1024K 2048K L2 data RAM input latency 1 cycle 2 cycles L2 data RAM output latency 2 cycles 3 cycles SCU L2 cache protection Included or not Advanced SIMD and Floating point Extension Included or not Cryptography Extension Included or not CPU cache p...

Page 19: ...entical configurations that were determined during the build configuration These configurations cannot be changed by software Either all of the cores have L1 cache protection or none have Either all of the cores have Advanced SIMD and Floating point Extensions or none have Either all of the cores have Cryptography Extensions or none have All cores must have the same size L1 caches as each other ...

Page 20: ...l rights reserved 1 9 ID021414 Non Confidential 1 6 Test features The Cortex A53 processor provides test signals that enable the use of both ATPG and MBIST to test the processor and its memory arrays See Appendix A Signal Descriptions for more information ...

Page 21: ...med before implementing the Cortex A53 processor The integrator to determine the pin configuration of the device that you are using There are separate TRMs for The optional Advanced SIMD and Floating point Extension The optional Cryptography Extension Configuration and Sign off Guide The Configuration and Sign off Guide CSG describes The available build configuration options and related issues in ...

Page 22: ...vior and features of the Cortex A53 processor The operation of the final device depends on Build configuration The implementer chooses the options that affect how the RTL source files are pre processed These options usually include or exclude logic that affects one or more of the area maximum frequency and features of the resulting macrocell Configuration inputs The integrator configures some feat...

Page 23: ...served 1 12 ID021414 Non Confidential 1 8 Product revisions This section describes the differences in functionality between product revisions r0p0 First release r0p1 There are no functional changes in this release r0p2 There are no functional changes in this release ...

Page 24: ...dential Chapter 2 Functional Description This chapter describes the functionality of the Cortex A53 processor It contains the following sections About the Cortex A53 processor functions on page 2 2 Interfaces on page 2 7 Clocking and resets on page 2 9 Power management on page 2 16 ...

Page 25: ...The IFU cannot hold A64 A32 and T32 instructions in the same cache line For example if the IFU fetches both A32 and T32 instructions from the same 64 byte region of memory that region occupies two cache lines one for the A32 instructions and one for the T32 instructions The instruction cache has the following features Pseudo random cache replacement policy L1 ICache L1 DCache Debug and trace Core ...

Page 26: ...gisters and a 3072 entry pattern history prediction table Return stack The IFU includes an 8 entry return stack to accelerate returns from procedure calls For each procedure call the return address is pushed onto a hardware stack When a procedure return is recognized the address held in the return stack is popped and the IFU uses it as the predicted return address The return stack is architectural...

Page 27: ...n table walk operations for the processor TLB entries are stored inside a 512 entry 4 way set associative RAM If the cache protection configuration is implemented the TLB RAMs are protected by parity bits The parity bits enable any single bit error to be detected If an error is detected the entry is flushed and fetched again See Chapter 6 Level 1 Memory System for more information 2 1 6 Data side ...

Page 28: ...IU to initiate linefills or request the BIU to write the data out on the external write channel External data writes are through the SCU The STB can merge Several store transactions into a single transaction if they are to the same 128 bit aligned address Multiple writes into an AXI or CHI write burst The STB is also used to queue maintenance operations before they are broadcast to other cores in ...

Page 29: ...53 processor supports cache protection in the form of ECC or parity on all RAM instances in the processor using two separate implementation options SCU L2 cache protection CPU cache protection These options enable the Cortex A53 processor to detect and correct a one bit error in any RAM and detect two bit errors in some RAMs 2 1 9 Debug and trace The Cortex A53 processor supports a range of debug ...

Page 30: ...nnect might be cores clusters I O bridges memory controllers or graphics processors See the ARM AMBA 5 CHI Protocol Specification 2 2 2 Accelerator Coherency Port The processor supports an Accelerator Coherency Port ACP This is an AMBA 4 AXI slave interface The ACP is provided to reduce software cache maintenance operations when sharing memory regions with other masters and to allow other masters ...

Page 31: ... implements a Design For Test DFT interface that enables an industry standard Automatic Test Pattern Generation ATPG tool to test logic outside of the embedded memories See DFT interface on page A 32 for information on these test signals 2 2 7 MBIST The Memory Built In Self Test MBIST controller interface provides support for manufacturing test of the memories embedded in the Cortex A53 processor ...

Page 32: ... is driven from CLKIN A separate enable signal PCLKENDBG is provided to enable the external APB bus to be driven at a lower frequency that must be an integer ratio of CLKIN If the debug infrastructure in the system is required to be fully asynchronous to the processor clock you can use a synchronizing component to connect the external AMBA APB to the processor Figure 2 2 shows a timing example of ...

Page 33: ...KM It is important that the relationship between ACLKM and ACLKENM is maintained If there are any physical effects that could occur while changing the clock frequency ARM recommends that the clock ratio is changed only while the STANDBYWFIL2 output of the processor is asserted The input signal ACLKENM exists in the Cortex A53 processor if it is configured to include the ACE interface ACLKENS This ...

Page 34: ...is configured to use the CHI protocol The SCU interface supports integer ratios of the CLKIN frequency for example 1 1 2 1 3 1 These ratios are configured through external clock enable signals In all cases CHI transfers remain synchronous The CHI master interface includes the SCLKEN clock enable signal Figure 2 5 shows a timing example of SCLKEN that changes the CLKIN to SCLK frequency ratio from ...

Page 35: ...hows a timing example of ATCLKEN that changes the CLKIN to ATCLK frequency ratio from 3 1 to 1 1 Figure 2 6 ATCLKEN with CLKIN ATCLK ratio changing from 3 1 to 1 1 Note Figure 2 6 shows the timing relationship between the ATB clock ATCLK and ATCLKENDBG where ATCLKENDBG asserts one clock cycle before the rising edge of ATCLK It is important that the relationship between ATCLK and ATCLKENDBG is main...

Page 36: ...ge of CLKIN It is important that the relationship between CLKIN and CNTCLKEN is maintained 2 3 2 Input synchronization The Cortex A53 processor synchronizes the input signals nCORERESET nCPUPORESET nFIQ nIRQ nL2RESET nMBISTRESET nPRESETDBG nREI nSEI nVFIQ nVIRQ nVSEI CLREXMONREQ CPUQREQn CTICHIN CTICHOUTACK CTIIRQACK DBGEN EDBGRQ EVENTI L2FLUSHREQ L2QREQn NEONQREQn NIDEN SPIDEN SPNIDEN CNTCLK CNTC...

Page 37: ...2 memory system and the logic in the SCU nMBISTRESET An external MBIST controller can use this signal to reset the entire SoC The nMBISTRESET signal resets all resettable registers in the cluster for entry into and exit from MBIST mode All of these resets can be asynchronously Asserted HIGH to LOW Deasserted LOW to HIGH Reset synchronisation logic inside the Cortex A53 processor ensures that reset...

Page 38: ...ESET CN 0 nCORERESET CN 0 nPRESETDBG nL2RESET nMBISTRESET n 0a n Xa 1 1 1 Individual core is held in reset so that the core can be powered up This enables external debug over power down for the core that is held in reset Individual core warm reset with trace and debug active nCPUPORESET CN 0 nCORERESET CN 0 nPRESETDBG nL2RESET nMBISTRESET n 1 n 0 1 1 1 Individual core is held in reset Debug logic ...

Page 39: ...owered down This means the Cortex A53 processor can continue to accept snoops from external devices to access the L2 cache Figure 2 8 on page 2 17 shows an example of the domains embedded in a System on Chip SoC power domain Table 2 2 Power domain description Power domain Description PDCORTEXA53 This includes the SCU the optional L2 cache controller and debug registers described as being in the de...

Page 40: ... terms used are defined in Table 2 3 Caution States not shown in Table 2 4 on page 2 18 and Table 2 5 on page 2 18 are unsupported and must not occur System PDSOC Cortex A53 processor PDCORTEXA53 L2 PDL2 Core n PDCPU n Core n excluding RAM APB Master Interface Data cache RAM ATB Instruction cache RAM TLB RAM If implementation includes Dormant mode support Advanced SIMD and Floating point L2 exclud...

Page 41: ... the processor functionality is available The Cortex A53 processor uses gated clocks and gates to disable inputs to unused functional blocks Only the logic in use to perform an operation consumes any dynamic power Table 2 4 Supported processor power states Power domains Description PDCORTEXA53 PDL2 PDCPU n Off Off Off Cluster off L2 RAMs and all cores are off Off On Ret Off L2 Dormant mode L2 RAMs...

Page 42: ... Load instructions Cache and TLB maintenance operations Store exclusive instructions In addition the WFI instruction ensures that store instructions have updated the cache or have been issued to the SCU While the core is in WFI low power state the clocks in the core are temporarily enabled without causing the core to exit WFI low power state when any of the following events are detected A snoop re...

Page 43: ...ing in the core power domain Exit from WFE low power state occurs when the core detects a reset the assertion of the EVENTI input signal or one of the WFE wake up events as described in the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile On entry into WFE low power state STANDBYWFE for that core is asserted Assertion of STANDBYWFE guarantees that the core is in idle and lo...

Page 44: ... on the ACP interface When the L2 memory system completes the outstanding transactions for AXI or CHI interfaces it can then enter the low power state L2 WFI low power state On entry into L2 WFI low power state STANDBYWFIL2 is asserted Assertion of STANDBYWFIL2 guarantees that the L2 memory system is idle and does not accept new transactions Exit from L2 WFI low power state occurs on one of the fo...

Page 45: ...egister changes from the previous steps have been committed 5 Execute a DSB SY instruction to ensure that all cache TLB and branch predictor maintenance operations issued by any core in the cluster device before the SMPEN bit was cleared have completed 6 Execute a WFI instruction and wait until the STANDBYWFI output is asserted to indicate that the core is in idle and low power state 7 Deassert DB...

Page 46: ...er assert nCPUPORESET LOW 2 Assert nL2RESET LOW and hold L2RSTDISABLE LOW 3 Apply power to the PDCORTEXA53 and PDL2 domains while keeping the signals described in steps 1 and 2 LOW 4 Release the cluster output clamps 5 Continue a normal cold reset sequence Cluster shutdown mode with system driven L2 flush This is the mode where the PDCORTEXA53 PDL2 and PDCPU power domains are shut down and all sta...

Page 47: ...he cluster excluding the contents of the L2 cache RAMs that remain powered up must be saved to external memory To exit from Dormant mode to Normal state the SoC must perform a cold reset sequence The SoC must assert the reset signals until power is restored After power is restored the cluster exits the cold reset sequence and the architectural state must be restored To enter Dormant mode apply the...

Page 48: ...at L2 memory system is idle All Cortex A53 processor implementations contain an L2 memory system including implementations without an L2 cache 11 When all cores STANDBYWFI and STANDBYWFIL2 are asserted the cluster is ready to enter Dormant mode 12 Activate the L2 cache RAM input clamps 13 Remove power from the PDCPU and PDCORTEXA53 power domains To exit Dormant mode apply the following sequence 1 ...

Page 49: ...WFI n signal indicates when an individual core is in idle and low power state The power management controller can remove power from an individual core when STANDBYWFI n is asserted See Individual core shutdown mode on page 2 21 for more information The STANDBYWFIL2 signal indicates when all individual cores and the L2 memory system are in idle and low power state A power management controller can ...

Page 50: ...typically of but not restricted to clock gated and power gated retention states of the device or device partitions The capability to indicate a requirement for exit from the quiescent state The associated signalling can contain contributions from other devices dependent on the interfaced device s operations Optional device capability to deny a quiescence request Safe asynchronous interfacing acros...

Page 51: ...on Confidential Chapter 3 Programmers Model This chapter describes the processor registers and provides information for programming the Cortex A53 processor It contains the following sections About the programmers model on page 3 2 ARMv8 A architecture concepts on page 3 4 ...

Page 52: ...elle implementation on page 3 3 Modes of operation on page 3 3 3 1 1 Advanced SIMD and Floating point support Advanced SIMD is a media and signal processing architecture that adds instructions targeted primarily at audio video 3 D graphics image and speech processing Floating point performs single precision and double precision floating point operations Note Advanced SIMD its associated implementa...

Page 53: ...es not accelerate the execution of any bytecodes and the JVM uses software routines to execute all bytecodes See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for information 3 1 4 Modes of operation In AArch32 the processor has the following instruction set operating states controlled by the T bit and J bit in the CPSR A32 The processor executes 32 bit word aligned ...

Page 54: ...s model The execution states are AArch64 The 64 bit execution state This execution state Features 31 64 bit general purpose registers with a 64 bit Program Counter PC Stack Pointer SP and Exception Link Registers ELRs Provides a single instruction set A64 For more information see Instruction set state on page 3 10 Defines the ARMv8 exception model with four exception levels EL0 EL3 that provide an...

Page 55: ...rom 1 to 3 indicate increased software execution privilege EL2 provides support for processor virtualization EL3 provides support for a secure state see Security state on page 3 6 The Cortex A53 processor implements all the Exception levels EL0 EL3 and supports both Execution states AArch64 and AArch32 at each Exception level Execution can move between Exception levels only on taking an exception ...

Page 56: ...ther Exception level is described as being a lower Exception level than the other Exception level For example EL0 is a lower Exception level than EL1 An Exception level is described as Using AArch64 when execution in that Exception level is in the AArch64 Execution state Using AArch32 when execution in that Exception level is in the AArch32 Execution state Typical exception level usage model The a...

Page 57: ...on level Note The execution state cannot change if on taking an exception or on returning from an exception the exception level remains the same On taking an exception to a higher exception level the execution state Can either Remain the same Increase from AArch32 state to AArch64 state Cannot decrease from AArch64 state to AArch32 state On returning from an exception to a lower exception level th...

Page 58: ...of the stack pointer are FIQ mode IRQ mode Supervisor mode Abort mode Undefined mode Hyp mode and Monitor mode Software executing in User mode or System mode uses the User mode stack pointer SP_usr For more information see AArch32 execution modes on page 3 10 3 2 6 ARMv8 security model The Cortex A53 processor implements all of the exception levels This means EL3 exists only in Secure state and a ...

Page 59: ...tation where EL3 is using AArch32 the security model is as shown in Figure 3 2 on page 3 10 This figure also shows the expected use of the different exception levels and processor modes Secure App2 Secure App1 App2 App1 App2 App1 AArch32 or AArch64 Guest OS1 AArch32 or AArch64 AArch32 or AArch64 AArch32 or AArch64 AArch32 or AArch64 AArch32 or AArch64 AArch32 or AArch64 Guest OS2 AArch32 or AArch6...

Page 60: ...ction of ARMv8 it was called the ARM instruction set T32 This is a variable length instruction set that uses both 16 bit and 32 bit instruction encodings Before the introduction of ARMv8 it was called the Thumb instruction set state 3 2 8 AArch32 execution modes ARMv7 and earlier versions of the ARM architecture define a set of named processor modes including modes that correspond to different exc...

Page 61: ...ty state To distinguish between a mode in Secure state and the equivalent mode in Non secure state the mode name is qualified as Secure or Non secure For example a description of AArch32 operation in EL1 might reference the Secure FIQ mode or to the Non secure FIQ mode Table 3 3 AArch32 processor modes and associated exception levels AArch32 processor mode EL3 using Security state Exception level ...

Page 62: ...s chapter describes the system registers their structure operation and how to use them It contains the following sections About system control on page 4 2 AArch64 register summary on page 4 3 AArch64 register descriptions on page 4 14 AArch32 register summary on page 4 135 AArch32 register descriptions on page 4 157 ...

Page 63: ...h32 Execution state are described in the AArch32 register descriptions on page 4 157 Some of the system registers can be accessed through the memory mapped or external debug interfaces Bits in the system registers that are described in the ARMv7 architecture are redefined in the ARMv8 A architecture UNK SBZP RAZ SBZP and RAZ WI are redefined as RES0 UNK SBOP and RAO SBOP are redefined as RES1 RES0...

Page 64: ...set to 0x00000000 for all 64 bit registers in Table 4 1 Table 4 1 AArch64 identification registers Name Type Reset Width Description MIDR_EL1 RO 0x410FD032 32 Main ID Register EL1 on page 4 14 MPIDR_EL1 RO a 64 Multiprocessor Affinity Register on page 4 15 REVIDR_EL1 RO 0x00000000 32 Revision ID Register on page 4 16 ID_PFR0_EL1 RO 0x00000131 32 AArch32 Processor Feature Register 0 on page 4 17 ID...

Page 65: ... Cache Level ID Register on page 4 44 AIDR_EL1 RO 0x00000000 32 Auxiliary ID Register on page 4 45 CSSELR_EL1 RW 0x00000000 32 Cache Size Selection Register on page 4 45 CTR_EL0 RO 0x84448004 32 Cache Type Register on page 4 47 DCZID_EL0 RO 0x00000004 32 Data Cache Zero ID Register on page 4 48 VPIDR_EL2 RW 0x410FD032 32 Virtualization Processor ID Register on page 4 49 VMPIDR_EL2 RO i 64 Virtuali...

Page 66: ...1 EL2 and EL3 on page 4 97 AFSR1_EL2 RW 0x00000000 32 Auxiliary Fault Status Register 1 EL1 EL2 and EL3 on page 4 97 ESR_EL2 RW UNK 32 Exception Syndrome Register EL2 on page 4 101 AFSR0_EL3 RW 0x00000000 32 Auxiliary Fault Status Register 0 EL1 EL2 and EL3 on page 4 97 AFSR1_EL3 RW 0x00000000 32 Auxiliary Fault Status Register 1 EL1 EL2 and EL3 on page 4 97 ESR_EL3 RW UNK 32 Exception Syndrome Re...

Page 67: ...zation Translation Table Base Address Register EL2c VTCR_EL2 RW UNK 32 Virtualization Translation Control Register EL2 on page 4 91 TTBR0_EL3 RW UNK 64 Translation Table Base Register 0 EL3 on page 4 93 TCR_EL3 RW UNK 32 Translation Control Register EL3 on page 4 94 MAIR_EL1 RW UNK 64 Memory Attribute Indirection Register EL1 on page 4 116 AMAIR_EL1 RW 0x00000000 64 Auxiliary Memory Attribute Indi...

Page 68: ...r on page 12 7 PMCNTENSET_EL0 RW UNK 32 Performance Monitors Count Enable Set Registera PMCNTENCLR_EL0 RW UNK 32 Performance Monitors Count Enable Clear Registera PMOVSCLR_EL0 RW UNK 32 Performance Monitors Overflow Flag Status Clear Registera PMSWINC_EL0 WO 32 Performance Monitors Software Increment Registera PMSELR_EL0 RW UNK 32 Performance Monitors Event Counter Selection Registera PMCEID0_EL0 ...

Page 69: ... RW UNK 32 PMEVTYPER4_EL0 RW UNK 32 PMEVTYPER5_EL0 RW UNK 32 PMCCFILTR_EL0 RW 0x00000000 32 Performance Monitors Cycle Count Filter Registera a See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for more information b The reset value is 0x663FBFFF if the Cortex A53 processor has not been configured with an L2 cache Table 4 5 AArch64 performance monitor registers conti...

Page 70: ...R_EL3 RW 0x0000000000000000 64 Vector Base Address Register EL3 on page 4 121 a Reset value is 0x00000000 if Advanced SIMD and Floating point are implemented 0x00000400 otherwise Table 4 8 AArch64 virtualization registers Name Type Reset Width Description VPIDR_EL2 RW 0x410FD031 32 Virtualization Processor ID Register on page 4 49 VMPIDR_EL2 RW a 64 Virtualization Multiprocessor ID Register on pag...

Page 71: ...value of the Multiprocessor Affinity Register b The reset value depends on inputs CFGTE and CFGEND The value shown assumes these signals are set to LOW c Reset value is 0x0000BFFF if Advanced SIMD and Floating point are not implemented d See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for more information Table 4 8 AArch64 virtualization registers continued Name Ty...

Page 72: ...g Priority Register ICC_SEIEN_EL1 RW 0x00000000 32 System Error Interrupt Enable Register ICC_SGI0R_EL1 WO 64 SGI Generation Register 0 ICC_SGI1R_EL1 WO 64 SGI Generation Register 1 ICC_SRE_EL1 RW 0x00000000 32 System Register Enable Register for EL1 ICC_SRE_EL2 RW 0x00000000 32 System Register Enable Register for EL2 ICC_SRE_EL3 RW 0x00000000 32 System Register Enable Register for EL3 a This is t...

Page 73: ...ary Fault Status Register 0 EL1 EL2 and EL3 on page 4 97 AFSR1_EL3 RW 0x00000000 32 Auxiliary Fault Status Register 1 EL1 EL2 and EL3 on page 4 97 AMAIR_EL1 RW 0x00000000 64 Auxiliary Memory Attribute Indirection Register EL1 EL2 and EL3 on page 4 97 AMAIR_EL2 RW 0x00000000 64 Auxiliary Memory Attribute Indirection Register EL1 EL2 and EL3 on page 4 97 AMAIR_EL3 RW 0x00000000 64 Auxiliary Memory A...

Page 74: ...4 13 ID021414 Non Confidential 4 2 13 AArch64 address registers Table 4 12 shows the address translation register in AArch64 state Table 4 12 AArch64 address translation register Name Type Reset Width Description PAR_EL1 RW UNK 64 Physical Address Register EL1 on page 4 112 ...

Page 75: ... bit register Figure 4 1 shows the MIDR_EL1 bit assignments Figure 4 1 MIDR_EL1 bit assignments Table 4 13 shows the MIDR_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO Variant Implementer 31 23 20 19 16 15 4 3 0 Architecture PartNum Revision 24 Table 4 13 MIDR_EL1 bit assignments Bits Name Function 31 24 Implementer Indicates the implementer code This value is 0...

Page 76: ...ng purposes in a cluster system Usage constraints This register is accessible as follows Configurations The MPIDR_EL1 31 0 is Architecturally mapped to the AArch32 MPIDR register See Multiprocessor Affinity Register on page 4 158 Mapped to external EDDEVAFF0 register MPIDR_EL1 63 32 is mapped to external EDDEVAFF1 register Attributes MPIDR_EL1 is a 64 bit register Figure 4 2 shows the MPIDR_EL1 bi...

Page 77: ... 30 U Indicates a single core system as distinct from core 0 in a cluster This value is 0 Core is part of a cluster 29 25 Reserved RES0 24 MT Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi threading type approach This value is 0 Performance of cores at the lowest affinity level is largely independent 23 16 Aff2 Affinity level 2 Second hi...

Page 78: ... Register access is encoded as follows 4 3 4 AArch32 Processor Feature Register 0 The ID_PFR0_EL1 characteristics are Purpose Gives top level information about the instruction sets supported by the processor in AArch32 Usage constraints This register is accessible as follows EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO 31 0 ID number Table 4 17 REVIDR_EL1 bit assignments Bits Name...

Page 79: ...sor Usage constraints This register is accessible as follows 31 12 11 8 7 0 RES0 State2 State1 16 15 4 3 State0 State3 Table 4 19 ID_PFR0_EL1 bit assignments Bits Name Function 31 16 Reserved RES0 15 12 State3 Indicates support for Thumb Execution Environment T32EE instruction set This value is 0x0 Processor does not support the T32EE instruction set 11 8 State2 Indicates support for Jazelle This ...

Page 80: ...11 8 7 0 GIC CPU 4 3 16 15 Virtualization 20 19 23 24 27 28 Reserved GenTimer MProgMod Security ProgMod Table 4 21 ID_PFR1_EL1 bit assignments Bits Name Function 31 28 GIC CPU GIC CPU support 0x0 GIC CPU interface is disabled GICCDISABLE is HIGH 0x1 GIC CPU interface is enabled 27 20 Reserved RES0 19 16 GenTimer Generic Timer support 0x1 Generic Timer supported 15 12 Virtualization Virtualization ...

Page 81: ...its Name Function 31 28 Reserved RES0 27 24 PerfMon Indicates support for performance monitor model 0x3 Support for Performance Monitor Unit version 3 PMUv3 system registers 23 20 MProfDbg Indicates support for memory mapped debug model for M profile processors 0x0 Processor does not support M profile Debug architecture 19 16 MMapTrc Indicates support for memory mapped trace model 0x1 Support for ...

Page 82: ...port in AArch32 Usage constraints This register is accessible as follows Configurations ID_MMFR0_EL1 is architecturally mapped to AArch32 register ID_MMFR0 See Memory Model Feature Register 0 on page 4 165 Attributes ID_MMFR0_EL1 is a 32 bit register Figure 4 7 shows the ID_MMFR0_EL1 bit assignments Figure 4 7 ID_MMFR0_EL1 bit assignments Table 4 24 REVIDR access encoding op0 op1 CRn CRm op2 1111 ...

Page 83: ...sion FCSE 0x0 Not supported 23 20 AuxReg Indicates support for Auxiliary registers 0x1 Support for Auxiliary Control Register only 19 16 TCM Indicates support for TCMs and associated DMAs 0x0 Not supported 15 12 ShareLvl Indicates the number of shareability levels implemented 0x1 Two levels of shareability implemented 11 8 OuterShr Indicates the outermost shareability domain implemented 0x1 Implem...

Page 84: ...time 27 24 L1TstCln Indicates the supported L1 Data cache test and clean operations for Harvard or unified cache implementation 0x0 None supported 23 20 L1Uni Indicates the supported entire L1 cache maintenance operations for a unified cache implementation 0x0 None supported 19 16 L1Hvd Indicates the supported entire L1 cache maintenance operations for a Harvard cache implementation 0x0 None suppo...

Page 85: ...sage constraints This register is accessible as follows Configurations ID_MMFR2_EL1 is architecturally mapped to AArch32 register ID_MMFR2 See Memory Model Feature Register 2 on page 4 168 Attributes ID_MMFR2_EL1 is a 32 bit register Figure 4 9 shows the ID_MMFR2_EL1 bit assignments Figure 4 9 ID_MMFR2_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO 31 12 11 8 7 0...

Page 86: ...ce operations are Invalidate all entries in the TLB Invalidate TLB entry by MVA Invalidate TLB entries by ASID match Invalidate instruction TLB and data TLB entries by MVA All ASID This is a shared unified TLB operation Invalidate Hyp mode unified TLB entry by MVA Invalidate entire Non secure EL1 and EL0 unified TLB Invalidate entire Hyp mode unified TLB TLBIMVALIS TLBIMVAALIS TLBIMVALHIS TLBIMVAL...

Page 87: ...straints This register is accessible as follows Configurations ID_MMFR3_EL1 is architecturally mapped to AArch32 register ID_MMFR3 See Memory Model Feature Register 3 on page 4 170 Attributes ID_MMFR3_EL1 is a 32 bit register Figure 4 10 shows the ID_MMFR3_EL1 bit assignments Figure 4 10 ID_MMFR3_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO 31 12 11 8 7 0 4 3 2...

Page 88: ...res according to shareability and defined behavior of instructions 11 8 BPMaint Branch predictor maintenance Indicates the supported branch predictor maintenance operations 0x2 Supported branch predictor maintenance operations are Invalidate all branch predictors Invalidate branch predictors by MVA 7 4 CMaintSW Cache maintenance by set way Indicates the supported cache maintenance operations by se...

Page 89: ... 27 24 23 20 19 16 15 12 11 8 7 4 3 0 RES0 Divide Debug Coproc CmpBranch Bitfield BitCount Swap Table 4 33 ID_ISAR0_EL1 bit assignments Bits Name Function 31 28 Reserved RES0 27 24 Divide Indicates the implemented Divide instructions 0x2 SDIV and UDIV in the T32 instruction set SDIV and UDIV in the A32 instruction set 23 20 Debug Indicates the implemented Debug instructions 0x1 BKPT 19 16 Coproc I...

Page 90: ... constraints This register is accessible as follows Configurations ID_ISAR1_EL1 is architecturally mapped to AArch32 register ID_ISAR1 See Instruction Set Attribute Register 1 on page 4 173 Attributes ID_ISAR1_EL1 is a 32 bit register Figure 4 12 shows the ID_ISAR1_EL1 bit assignments Figure 4 12 ID_ISAR1_EL1 bit assignments Table 4 34 ID_ISAR0_EL1 access encoding op0 op1 CRn CRm op2 11 000 0000 0...

Page 91: ... 20 Immediate Indicates the implemented data processing instructions with long immediates 0x1 The MOVT instruction The MOV instruction encodings with zero extended 16 bit immediates The T32 ADD and SUB instruction encodings with zero extended 12 bit immediates and other ADD ADR and SUB encodings cross referenced by the pseudocode for those encodings 19 16 IfThen Indicates the implemented If Then i...

Page 92: ...ally mapped to AArch32 register ID_ISAR2 See Instruction Set Attribute Register 2 on page 4 175 Attributes ID_ISAR2_EL1 is a 32 bit register Figure 4 13 shows the ID_ISAR2_EL1 bit assignments Figure 4 13 ID_ISAR2_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 MultiAccessInt Reversal PSR_AR MultU MultS Mult MemHint LoadSt...

Page 93: ...AAL instructions 19 16 MultS Indicates the implemented advanced signed Multiply instructions 0x3 The SMULL and SMLAL instructions The SMLABB SMLABT SMLALBB SMLALBT SMLALTB SMLALTT SMLATB SMLATT SMLAWB SMLAWT SMULBB SMULBT SMULTB SMULTT SMULWB SMULWT instructions and the Q bit in the PSRs The SMLAD SMLADX SMLALD SMLALDX SMLSD SMLSDX SMLSLD SMLSLDX SMMLA SMMLAR SMMLS SMMLSR SMMUL SMMULR SMUAD SMUADX...

Page 94: ... constraints This register is accessible as follows Configurations ID_ISAR3_EL1 is architecturally mapped to AArch32 register ID_ISAR3 See Instruction Set Attribute Register 3 on page 4 178 Attributes ID_ISAR3_EL1 is a 32 bit register Figure 4 14 shows the ID_ISAR3_EL1 bit assignments Figure 4 14 ID_ISAR3_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO TabBranch 3...

Page 95: ...g from a low register to a low register 19 16 TabBranch Indicates the implemented Table Branch instructions in the T32 instruction set 0x1 The TBB and TBH instructions 15 12 SynchPrim Indicates the implemented Synchronization Primitive instructions 0x2 The LDREX and STREX instructions The CLREX LDREXB STREXB and STREXH instructions The LDREXD and STREXD instructions 11 8 SVC Indicates the implemen...

Page 96: ...lemented M profile instructions to modify the PSRs 0x0 None implemented 23 20 SynchPrim_frac This field is used with the ID_ISAR3 SynchPrim field to indicate the implemented Synchronization Primitive instructions 0x0 The LDREX and STREX instructions The CLREX LDREXB LDREXH STREXB and STREXH instructions The LDREXD and STREXD instructions 19 16 Barrier Indicates the supported Barrier instructions i...

Page 97: ... of the processor ARM requires licensees to have contractual rights to obtain the Advanced SIMD and Floating point extension Usage constraints This register is accessible as follows Configurations ID_ISAR5_EL1 is architecturally mapped to AArch32 register ID_ISAR5 See Instruction Set Attribute Register 5 on page 4 181 Attributes ID_ISAR5_EL1 is a 32 bit register Figure 4 16 shows the ID_ISAR5_EL1 ...

Page 98: ... whether CRC32 instructions are implemented in AArch32 state 0x1 CRC32 instructions are implemented 15 12 SHA2 Indicates whether SHA2 instructions are implemented in AArch32 state 0x0 Cryptography Extensions are not implemented or are disabled 0x1 SHA256H SHA256H2 SHA256SU0 and SHA256SU1 instructions are implemented 11 8 SHA1 Indicates whether SHA1 instructions are implemented in AArch32 state 0x0...

Page 99: ...interface is disabled 0x1 GIC CPU interface is implemented 23 20 FPa Floating point The possible values are 0x0 Floating point is implemented 0xF Floating point is not implemented 19 16 AdvSIMDa Advanced SIMD The possible values are 0x0 Advanced SIMD is implemented 0xF Advanced SIMD is not implemented 15 12 EL3 handling EL3 exception handling 0x2 Instructions can be executed at EL3 in AArch64 or A...

Page 100: ...EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO 4 3 8 7 12 11 16 15 20 19 24 23 28 27 0 63 RES0 RES0 Debugger Tracever PMUver BRPs WRPs CTX_CMPs RES0 32 31 Table 4 47 ID_AA64DFR0_EL1 bit assignments Bits Name Function 63 32 Reserved RES0 31 28 CTX_CMPs Number of breakpoints that are context aware minus 1 These are the highest numbered breakpoints 0b0001 Two breakpoints are context aw...

Page 101: ...uded in the base product of the processor ARM requires licensees to have contractual rights to obtain the Cortex A53 Cryptography engine Usage constraints This register is accessible as follows Configurations ID_AA64ISAR0_EL1 is architecturally mapped to external register ID_AA64ISAR0_EL1 Attributes ID_AA64ISAR0_EL1 is a 64 bit register Figure 4 19 shows the ID_AA64ISAR0_EL1 bit assignments Figure...

Page 102: ...sabled 0b0001 SHA256H SHA256H2 SHA256U0 and SHA256U1 implemented This is the value if the implementation includes the Cryptography Extension All other values reserved 11 8 SHA1 Indicates whether SHA1 instructions are implemented The possible values are 0b0000 No SHA1 instructions implemented This is the value if the implementation does not include the Cryptography Extension 0b0001 SHA1C SHA1P SHA1...

Page 103: ...ments Bits Name Function 63 32 Reserved RES0 31 28 TGran4 Support for 4 KB memory translation granule size 0x0 Indicates that the 4KB granule is supported 27 24 TGran64 Support for 64 KB memory translation granule size 0x0 Indicates that the 64KB granule is supported 23 20 TGran16 Support for 16 KB memory translation granule size 0x0 Indicates that the 16KB granule is not supported 19 16 BigEndEL0...

Page 104: ...its Name Function 31 WT Indicates support for write through 0 Cache level does not support write through 30 WB Indicates support for write back 0 Cache level does not support write back 1 Cache level supports write back 29 RA Indicates support for Read Allocation 0 Cache level does not support Read Allocation 1 Cache level supports Read Allocation 28 WA Indicates support for Write Allocation 0 Cac...

Page 105: ... type of cache or caches implemented at each level The Level of Coherency and Level of Unification for the cache hierarchy Usage constraints This register is accessible as follows Configurations CLIDR_EL1 is architecturally mapped to AArch32 register CLIDR See Cache Level ID Register on page 4 185 Attributes CLIDR_EL1 is a 32 bit register Figure 4 22 shows the CLIDR_EL1 bit assignments Figure 4 22...

Page 106: ...ency operation requires the L1 cache to be cleaned 0b010 L2 cache implemented A clean to the point of coherency operation requires the L1 and L2 caches to be cleaned 23 21 LoUIS Indicates the Level of Unification Inner Shareable for the cache hierarchy 0b001 L2 cache L2 cache is the last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of unification fo...

Page 107: ...signments Table 4 57 shows the CSSELR_EL1 bit assignments To access the CSSELR_EL1 MRS Xt CSSELR_EL1 Read CSSELR_EL1 into Xt MSR CSSELR_EL1 Xt Write Xt to CSSELR_EL1 Register access is encoded as follows EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW InD UNK SBZP 31 4 3 1 0 Level Table 4 57 CSSELR_EL1 bit assignments Bits Name Function 31 4 Reserved RES0 3 1 Levela a The combination...

Page 108: ...eserved RES1 30 28 Reserved RES0 27 24 CWG Cache Write Back granule Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified 0x4 Cache Write Back granule size is 16 words 23 20 ERG Exclusives Reservation Granule Log2 of the number of words of the maximum size of the reservation granu...

Page 109: ...es Attributes DCZID_EL0 is a 32 bit register Figure 4 25 shows the DCZID_EL0 bit assignments Figure 4 25 DCZID_EL0 bit assignments Table 4 61 shows the DCZID_EL0 bit assignments To access the DCZID_EL0 MRS Xt DCZID_EL0 Read DCZID_EL0 into Xt Table 4 60 CTR_EL0 access encoding op0 op1 CRn CRm op2 11 011 0000 0000 001 EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO RO 4 RES0 3 5 BlockS...

Page 110: ..._EL2 is a 32 bit register VPIDR_EL2 resets to the value of MIDR_EL1 Figure 4 26 shows the VPIDR_EL2 bit assignments Figure 4 26 VPIDR_EL2 bit assignments Table 4 63 shows the VPIDR_EL2 bit assignments To access the VPIDR_EL2 MRS Xt VPIDR_EL2 Read VPIDR_EL2 into Xt MSR VPIDR_EL2 Xt Write Xt to VPIDR_EL2 Register access is encoded as follows Table 4 62 DCZID_EL0 access encoding op0 op1 CRn CRm op2 1...

Page 111: ...nments Figure 4 27 VMPIDR_EL2 bit assignments Table 4 65 shows the VMPIDR_EL2 bit assignments To access the VMPIDR_EL2 MRS Xt VMPIDR_EL2 Read VMPIDR_EL2 into Xt MSR VMPIDR_EL2 Xt Write Xt to VMPIDR_EL2 Register access is encoded as follows 4 3 30 System Control Register EL1 The SCTLR_EL1 characteristics are Purpose Provides top level control of the system including its memory system at EL1 SCTLR_E...

Page 112: ... See System Control Register on page 4 191 Attributes SCTLR_EL1 is a 32 bit register Figure 4 28 shows the SCTLR_EL1 bit assignments Figure 4 28 SCTLR_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 31 0 M A C I RES0 SA CP15BEN ITD SED UMA SA0 RES0 RES0 EE DZE nTWI RES0 UCT E0E UCI THEE 25 26 24 23 20 18 19 17 16 15 13 14 12 11 10 8 9 7 6 5 3 4 2 1 27 28 29 30 RES...

Page 113: ... WXN Write permission implies Execute Never XN This bit can be used to require all memory regions with write permissions to be treated as XN The possible values are 0 Regions with write permission are not forced XN This is the reset value 1 Regions with write permissions are forced XN 18 nTWE WFE non trapping The possible values are 0 A WFE instruction executed at EL0 that if this bit was set to 1...

Page 114: ...ed 4 53 ID021414 Non Confidential 12 I Instruction cache enable The possible values are 0 Instruction caches disabled This is the reset value 1 Instruction caches enabled 11 Reserved RES1 10 Reserved RES0 Table 4 67 SCTLR_EL1 bit assignments continued Bits Name Function ...

Page 115: ...PC imm 0100x1xxx1111xxx ADD 4 CMP 3 MOV BX pc BLX pc 010001xx1xxxx111 ADD 4 CMP 3 MOV Contrary to the standard treatment of conditional UNDEFINED instructions in the ARM architecture in this case these instructions are always treated as UNDEFINED regardless of whether the instruction would pass or fail its condition codes as a result of being in an IT block 6 THEE RES0 T32EE is not implemented 5 C...

Page 116: ...TLR Usage constraints This register is accessible as follows Configurations The ACTLR_EL2 is architecturally mapped to the AArch32 HACTLR register See Hyp Auxiliary Control Register on page 4 205 Attributes ACTLR_EL2 is a 32 bit register Figure 4 29 shows the ACTLR_EL2 bit assignments Figure 4 29 ACTLR_EL2 bit assignments 0 M MMU enable The possible values are 0 EL1 and EL0 stage 1 MMU disabled Th...

Page 117: ...L2ECTLR access control L2ECTLR_EL1 write access control The possible values are 0 The register is not write accessible from Non secure EL1 This is the reset value 1 The register is write accessible from Non secure EL1 Write access from Non secure EL1 also requires ACTLR_EL3 5 to be set 4 L2CTLR access control L2CTLR_EL1 write access control The possible values are 0 The register is not write acces...

Page 118: ...l The possible values are 0 The register is not write accessible from a lower exception level This is the reset value 1 The register is write accessible from EL2 5 L2ECTLR access control L2ECTLR_EL1 write access control The possible values are 0 The register is not write accessible from a lower exception level This is the reset value 1 The register is write accessible from EL2 4 L2CTLR access cont...

Page 119: ...system including its memory system at EL2 EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 31 0 RES0 TTA RES0 FPEN 19 28 27 20 21 22 29 RES0 Table 4 70 CPACR_EL1 bit assignments Bits Name Function 31 29 Reserved RES0 28 TTA Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1 This bit is RES0 27 22 Reserved RES0 21 20 FPEN Traps instructions that acces...

Page 120: ...EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW 31 0 EE 25 26 20 RES1 19 18 12 11 2 1 4 3 WXN I C A M SA RES0 30 29 28 27 RES1 RES0 24 23 RES0 22 21 RES0 17 16 15 14 13 RES1 RES0 RES1 RES0 10 6 5 RES0 RES1 RES1 Table 4 71 SCTLR_EL2 bit assignments Bits Name Function 31 30 Reserved RES0 29 28 Reserved RES1 27 26 Reserved RES0 25 EE Exception endianness The possible values are 0 Little endia...

Page 121: ...ES0 12 I Instruction cache enable The possible values are 0 Instruction caches disabled This is the reset value 1 Instruction caches enabled 11 Reserved RES1 10 6 Reserved RES0 5 4 Reserved RES1 3 SA Enables stack alignment check The possible values are 0 Disables stack alignment check 1 Enables stack alignment check This is the reset value 2 C Global enable for data and unifies caches The possibl...

Page 122: ...ion Register 2 on page 4 216 Attributes HCR_EL2 is a 64 bit register Figure 4 33 shows the HCR_EL2 bit assignments Figure 4 33 HCR_EL2 bit assignments 31 0 1 2 11 12 TRVM RW PTW FMO IMO AMO VF VI VSE FB BSU DC TWI TWE TID0 HCD TDZ TGE TVM TTLB TPU TSW TACR TIDCP TSC TID3 TID2 TID1 TPC SWIO VM 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 RES0 32 33 34 CD ID 63 ...

Page 123: ... AArch64 EL0 is determined by the register width described in the current processing state when executing at EL0 30 TRVM Trap reads of Virtual Memory controls a The possible values are 0 Non secure EL1 reads are not trapped This is the reset value 1 Non secure EL1 reads are trapped to EL2 29 HCD Reserved RES0 28 TDZ Traps DC ZVA instruction The possible values are 0 DC ZVA instruction is not trapp...

Page 124: ...ction set space executed from Non secure EL1 to be trapped to EL2 AArch32 All CP15 MCR and MRC instructions as follows CRn is 9 Opcode1 is 0 to 7 CRm is c0 c1 c2 c5 c6 c7 or c8 and Opcode2 is 0 to 7 CRn is 10 Opcode1 is 0 to 7 CRm is c0 c1 c4 or c8 and Opcode2 is 0 to 7 CRn is 11 Opcode1 is 0 to 7 CRm is c0 to c8 or c15 and Opcode2 is 0 to 7 AArch64 Reserved control space for IMPLEMENTATION DEFINE...

Page 125: ...rch64 Execution states 12 DC Default cacheable When this bit is set it causes SCTLR_EL1 M to behave as 0 for all purposes other than reading the bit HCR_EL2 VM to behave as 1 for all purposes other than reading the bit The memory type produced by the first stage of translation in Non secure EL1 and EL0 is Non Shareable Inner Write Back Write Allocate Outer Write Back Write Allocate The reset value...

Page 126: ...r lower are taken in EL2 unless routed by SCTLR_EL3 EA bit to EL3 Virtual System Error Asynchronous Abort is enabled 4 IMO Physical IRQ routing The possible values are 0 Physical IRQ while executing at exception levels lower than EL2 are not taken at EL2 Virtual IRQ interrupt is disabled This is the reset value 1 Physical IRQ while executing at EL2 or lower are taken in EL2 unless routed by SCTLR_...

Page 127: ... follows Configurations MDCR_EL2 is architecturally mapped to AArch32 register HDCR See Hyp Debug Control Register on page 4 217 This register is accessible only at EL2 or EL3 Attributes MDCR_EL2 is a 32 bit register Figure 4 34 shows the MDCR_EL2 bit assignments Figure 4 34 MDCR_EL2 bit assignments a See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for the register...

Page 128: ...SystemControl ARM DDI 0500D Copyright 2013 2014 ARM All rights reserved 4 67 ID021414 Non Confidential Table 4 73 on page 4 68 shows the MDCR_EL2 bit assignments ...

Page 129: ...reset the field resets to 0 9 TDA Trap Debug Access 0 Has no effect on accesses to Debug registers 1 Trap valid Non secure accesses to Debug registers to EL2 When this bit is set to 1 any valid Non secure access to the debug registers from EL1 or EL0 other than the registers trapped by the TDRA and TDOSA bits is trapped to EL2 If HCR_EL2 TGE is 1 or MDCR_EL2 TDE is1 then this bit is ignored and tr...

Page 130: ...ation 4 0 HPMN Hyp Performance Monitor count Defines the number of Performance Monitors counters that are accessible from Non secure EL1 and EL0 modes In Non secure state HPMN divides the Performance Monitors counters as follows For counter n in Non secure state For example If PMnEVCNTR is performance monitor counter n then in Non secure state If n is in the range 0 n HPMN the counter is accessibl...

Page 131: ...1 RES0 TTA 13 12 14 RES1 RES0 30 Table 4 74 CPTR_EL2 bit assignments Bits Name Function 31 TCPAC Traps direct access to CPACR from Non secure EL1 to EL2 The possible values are 0 Access to CPACR is not trapped This is the reset value 1 Access to CPACR is trapped 30 21 Reserved RES0 20 TTA Trap Trace Access Not implemented RES0 19 14 Reserved RES0 13 12 Reserved RES1 11 Reserved RES0 10 TFP Traps i...

Page 132: ...d 4 71 ID021414 Non Confidential Attributes HSTR_EL2 is a 32 bit register Figure 4 36 shows the HSTR_EL2 bit assignments Figure 4 36 HSTR_EL2 bit assignments 31 0 RES0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TTEE RES0 T15 T13 T12 T11 T10 T9 T8 T0 T1 T2 T3 RES0 T5 T6 T7 ...

Page 133: ...e accesses to CP15 registers 1 Trap valid Non secure accesses to coprocessor primary register CRn 13 to Hyp mode The reset value is 0 12 T12 Trap coprocessor primary register CRn 12 The possible values are 0 Has no effect on Non secure accesses to CP15 registers 1 Trap valid Non secure accesses to coprocessor primary register CRn 12 to Hyp mode The reset value is 0 11 T11 Trap coprocessor primary ...

Page 134: ...gister CRn 6 to Hyp mode The reset value is 0 5 T5 Trap coprocessor primary register CRn 5 The possible values are 0 Has no effect on Non secure accesses to CP15 registers 1 Trap valid Non secure accesses to coprocessor primary register CRn 5 to Hyp mode The reset value is 0 4 Reserved RES0 3 T3 Trap coprocessor primary register CRn 3 The possible values are 0 Has no effect on Non secure accesses ...

Page 135: ...R_EL3 is part of the Virtual memory control registers functional group Usage constraints This register is accessible as follows Configurations SCTLR_EL3 is mapped to AArch32 register SCTLR S See System Control Register on page 4 191 Attributes SCTLR_EL3 is a 32 bit register Figure 4 37 shows the SCTLR_EL3 bit assignments Figure 4 37 SCTLR_EL3 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 S...

Page 136: ...value 1 Regions with write permissions are forced XN 18 Reserved RES1 17 Reserved RES0 16 Reserved RES1 15 13 Reserved RES0 12 I Global instruction cache enable The possible values are 0 Instruction caches disabled This is the reset value 1 Instruction caches enabled 11 Reserved RES1 10 6 Reserved RES0 5 4 Reserved RES1 3 SA Enables stack alignment check The possible values are 0 Disables stack al...

Page 137: ...width at lower exception levels The exception level that the processor takes exceptions at if an IRQ FIQ or external abort occurs SCR_EL3 is part of the Security registers functional group Usage constraints This register is accessible as follows Configurations SCR_EL3 is mapped to AArch32 register SCR See Secure Configuration Register on page 4 199 Attributes SCR_EL3 is a 32 bit register Figure 4 ...

Page 138: ...or EL1 See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for more information 12 TWI Traps WFI instructions The possible values are 0 WFI instructions are not trapped This is the reset value 1 WFI instructions executed in AArch32 or AArch64 from EL2 EL1 or EL0 are trapped to EL3 if the instruction would otherwise cause suspension of execution that is if there is not ...

Page 139: ...enabled at EL1 EL2 and EL3 This is the reset value 1 The SMC instruction is UNDEFINED at all exception levels At EL1 in the Non secure state the HCR_EL2 TSC bit has priority over this control 6 Reserved RES0 5 4 Reserved RES1 3 EA External Abort and SError interrupt Routing This bit controls which mode takes external aborts The possible values are 0 External Aborts and SError Interrupts while exec...

Page 140: ...base address of translation table 0 and information about the memory it occupies This is one of the translation tables for the stage 1 translation of memory accesses from modes other than Hyp mode Usage constraints This register is accessible as follows EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW 31 0 RES0 SUNIDEN SUIDEN 1 2 Table 4 78 SDER32_EL3 bit assignments Bits Name Function 31 2 Re...

Page 141: ... the fields in this register are permitted to be cached in a TLB Configurations TTBR1_EL1 is architecturally mapped to AArch32 register TTBR1 NS See Translation Table Base Register 1 on page 4 226 BADDR 47 x ASID 47 48 0 63 Table 4 79 TTBR0_EL1 bit assignments Bits Name Function 63 48 ASID An ASID for the translation table base address The TCR_EL1 A1 field selects either TTBR0_EL1 ASID or TTBR1_EL...

Page 142: ...es Attributes CPTR_EL3 is a 32 bit register Figure 4 42 on page 4 82 shows the CPTR_EL3 bit assignments BADDR 47 x ASID 47 48 0 63 Table 4 80 TTBR1_EL1 bit assignments Bits Name Function 63 48 ASID An ASID for the translation table base address The TCR_EL1 A1 field selects either TTBR0_EL1 ASID or TTBR1_EL1 ASID 47 0 BADDR 47 x Translation table base address bits 47 x Bits x 1 0 are RES0 x is base...

Page 143: ...L1 or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2 The possible values are 0 Does not cause access to the CPACR_EL1 or CPTR_EL2 to be trapped 1 Causes access to the CPACR_EL1 or CPTR_EL2 to be trapped 30 21 Reserved RES0 20 TTA Trap Trace Access Not implemented RES0 19 14 Reserved RES0 13 12 Reserved RES1 11 Reserved RES0 10 TFP This causes instructions that access the register...

Page 144: ... 4 83 ID021414 Non Confidential Attributes MDCR_EL3 is a 32 bit register Figure 4 43 shows the MDCR_EL3 bit assignments Figure 4 43 MDCR_EL3 bit assignments 31 0 RES0 TPM 20 19 21 22 16 15 17 18 14 13 11 10 9 6 7 8 5 RES0 TDA TDOSA SPD32 SDD SPME EDAD EPMAD RES0 RES0 RES0 ...

Page 145: ...re 0 Access to Performance Monitors registers from external debugger is permitted 1 Access to Performance Monitors registers from external debugger is disabled unless overridden by authentication interface 20 EDAD External debugger access to breakpoint and watchpoint registers disabled This disables access to these registers by an external debugger The possible values are 0 Access to breakpoint an...

Page 146: ...sables debug exceptions from Secure state if Secure EL1 is using AArch32 other than Software breakpoint instructions The possible values are 0b00 Legacy mode Debug exceptions from Secure EL1 are enabled only if AArch32SelfHostedSecurePrivilegedInvasiveDebugEnabled 0b01 Reserved 0b10 Secure privileged debug disabled Debug exceptions from Secure EL1 are disabled 0b11 Secure privileged debug enabled ...

Page 147: ... part of the Virtual memory control registers functional group Usage constraints This register is accessible as follows Configurations TCR_EL1 is architecturally mapped to AArch32 register TTBCR NS See Hyp Translation Control Register on page 4 232 Attributes TCR_EL1 is a 64 bit register Figure 4 44 shows the TCR_EL1 bit assignments Figure 4 44 TCR_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR ...

Page 148: ...in the address calculation 36 AS ASID size The possible values are 0 8 bit 1 16 bit 35 Reserved RES0 34 32 IPS Intermediate Physical Address Size The possible values are 0b000 32 bits 4 GB 0b001 36 bits 64 GB 0b010 40 bits 1 TB All other values are reserved 31 30 TG1 TTBR1_EL1 granule size The possible values are 0b00 4 KB 0b10 64 KB 29 28 SH1 Shareability attribute for memory associated with tran...

Page 149: ...defines the ASID 21 16 T1SZ Size offset of the memory region addressed by TTBR1_EL1 The region size is 2 64 T1SZ bytes 15 14 TG0 TTBR0_EL1 granule size The possible values are 0b00 4 KB 0b10 64 KB 13 12 SH0 Shareability attribute for memory associated with translation table walks using TTBR0_EL1 The possible values are 0b00 Non shareable 0b01 Reserved 0b10 Outer shareable 0b11 Inner shareable 11 1...

Page 150: ... registers functional group The Hypervisor and virtualization registers functional group Usage constraints This register is accessible as follows Configurations TCR_EL2 is architecturally mapped to AArch32 register HCTR See Hyp Translation Control Register on page 4 232 Attributes TCR_EL2 is a 32 bit register Figure 4 45 shows the TCR_EL2 bit assignments Figure 4 45 TCR_EL2 bit assignments EL0 EL1...

Page 151: ...lity attribute for memory associated with translation table walks using TTBR0_EL2 The possible values are 0b00 Non shareable 0b01 Reserved 0b10 Outer shareable 0b11 Inner shareable 11 10 ORGN0 Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2 The possible values are 0b00 Normal memory Outer Non cacheable 0b01 Normal memory Outer Write Back Write Alloca...

Page 152: ...ure EL0 and EL1 and holds cacheability and shareability information for the accesses Usage constraints This register is accessible as follows Any of the bits in VTCR_EL2 are permitted to be cached in a TLB Configurations VTCR_EL2 is architecturally mapped to AArch32 register VTCR See Virtualization Translation Control Register on page 4 233 Attributes VTCR_EL2 is a 32 bit register Figure 4 46 show...

Page 153: ...SH0 Shareability attribute for memory associated with translation table walks using VTTBR_EL2 0b00 Non shareable 0b01 Reserved 0b10 Outer Shareable 0b11 Inner Shareable 11 10 ORGN0 Outer cacheability attribute for memory associated with translation table walks using VTTBR_EL2 0b00 Normal memory Outer Non cacheable 0b01 Normal memory Outer Write Back Write Allocate Cacheable 0b10 Normal memory Oute...

Page 154: ...from EL3 Usage constraints This register is accessible as follows Configurations TTBR0_EL3 is mapped to AArch32 register TTBR0 S See Translation Table Base Register 0 on page 4 224 Attributes TTBR0_EL3 is a 64 bit register Figure 4 48 on page 4 94 shows the TTBR0_EL3 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ...

Page 155: ...ter TTBR S Attributes TCR_EL3 is a 32 bit register Figure 4 49 on page 4 95 shows the TCR_EL3 bit assignments BADDR 47 x RES0 47 48 0 63 Table 4 87 TTBR0_EL3 bit assignments Bits Name Function 63 48 Reserved RES0 47 0 BADDR 47 x Translation table base address bits 47 x Bits x 1 0 are RES0 x is based on the value of TCR_EL1 T0SZ the stage of translation and the memory translation granule size For i...

Page 156: ...3 bit assignments Table 4 88 shows the TCR_EL3 bit assignments RES0 31 30 24 23 22 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5 0 RES0 SH0 TG0 PS IRGN0 ORGN0 T0SZ RES0 TBI RES0 RES1 RES1 32 63 RES0 Table 4 88 TCR_EL3 bit assignments Bits Name Function 63 32 Reserved RES0 31 Reserved RES1 30 24 Reserved RES0 23 Reserved RES1 ...

Page 157: ... using TTBR0_EL3 The possible values are 0b00 Non shareable 0b01 Reserved 0b10 Outer shareable 0b11 Inner shareable 11 10 ORGN0 Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3 The possible values are 0b00 Normal memory Outer Non cacheable 0b01 Normal memory Outer Write Back Write Allocate Cacheable 0b10 Normal memory Outer Write Through Cacheable 0b1...

Page 158: ...atus Register 1 EL1 EL2 and EL3 The processor does not implement AFSR1_EL1 AFSR1_EL2 and AFSR1_EL3 therefore these registers are always RES0 4 3 57 Exception Syndrome Register EL1 The ESR_EL1 characteristics are Purpose Holds syndrome information for an exception taken to EL1 Usage constraints This register is accessible as follows Configurations ESR_EL1 is architecturally mapped to AArch32 regist...

Page 159: ...used This section describes IFSR when using the Short descriptor translation table format on page 4 243 IFSR when using the Long descriptor translation table format on page 4 244 IFSR32_EL2 when using the Short descriptor translation table format Figure 4 51 on page 4 99 shows the IFSR32_EL2 bit assignments when using the Short descriptor translation table format Table 4 89 ESR_EL1 bit assignments...

Page 160: ...rnal abort marked as SLVERR For aborts other than external aborts this bit always returns 0 11 Reserved RES0 10 FS 4 Part of the Fault Status field See bits 3 0 in this table 9 RAZ 8 5 Reserved RES0 4 0 FS 3 0 Fault Status bits This field indicates the type of exception generated Any encoding not listed is reserved 0b00010 Debug event 0b00011 Access flag fault section 0b00101 Translation fault sec...

Page 161: ...l abort marked as SLVERR For aborts other than external aborts this bit always returns 0 11 10 Reserved RES0 9 RAO 8 6 Reserved RES0 5 0 Status Fault Status bits This field indicates the type of exception generated Any encoding not listed is reserved 0b000000 Address size fault in TTBR0 or TTBR1 0b0001LL Translation fault LL bits indicate level 0b0010LL Access fault flag LL bits indicate level 0b0...

Page 162: ... Read IFSR32_EL2 into Xt MSR IFSR32_EL2 Xt Write Xt to IFSR32_EL2 Register access is encoded as follows 4 3 59 Exception Syndrome Register EL2 The ESR_EL2 characteristics are Purpose Holds syndrome information for an exception taken to EL2 Usage constraints This register is accessible as follows Configurations ESR_EL2 is architecturally mapped to AArch32 register HSR See Hyp Syndrome Register on p...

Page 163: ...ons ESR_EL3 is mapped to AArch32 register DFSR S See Data Fault Status Register on page 4 239 Attributes ESR_EL3 is a 32 bit register Figure 4 54 shows the ESR_EL3 bit assignments Figure 4 54 ESR_EL3 bit assignments Table 4 94 ESR_EL2 bit assignments Bits Name Function 31 26 EC Exception Class Indicates the reason for the exception that this register holds information about 25 IL Instruction Lengt...

Page 164: ...architecturally mapped to AArch32 register IFAR NS See Instruction Fault Address Register on page 4 248 Attributes FAR_EL1 is a 64 bit register Figure 4 55 shows the FAR_EL1 bit assignments Figure 4 55 FAR_EL1 bit assignments Table 4 95 ESR_EL3 bit assignments Bits Name Function 31 26 EC Exception Class Indicates the reason for the exception that this register holds information about 25 IL Instruc...

Page 165: ...AR See Hyp Data Fault Address Register on page 4 249 DFAR S See Data Fault Address Register on page 4 247 FAR_EL2 63 32 is architecturally mapped to AArch32 registers HIFAR See Hyp Instruction Fault Address Register on page 4 250 IFAR S See Instruction Fault Address Register on page 4 248 Attributes FAR_EL2 is a 64 bit register Figure 4 56 shows the FAR_EL2 bit assignments Figure 4 56 FAR_EL2 bit ...

Page 166: ...assignments Figure 4 57 HPFAR_EL2 bit assignments Table 4 98 on page 4 104shows the HPFAR_EL2 bit assignments To access the HPFAR_EL MRS Xt HPFAR_EL2 Read EL2 Fault Address Register MSR HPFAR_EL2 Xt Write EL2 Fault Address Register Table 4 97 FAR_EL2 bit assignments Bits Name Function 63 0 VA The faulting Virtual Address for all synchronous instruction or data aborts or an exception from a misalig...

Page 167: ...ister are ignored Configurations L2CTLR_EL1 is architecturally mapped to the AArch32 L2CTLR register See L2 Control Register on page 4 251 There is one L2CTLR_EL1 for the Cortex A53 processor Attributes L2CTLR_EL1 is a 32 bit register Figure 4 58 shows the L2CTLR_EL1 bit assignments Figure 4 58 L2CTLR_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 31 0 26 25 24 R...

Page 168: ...umber of cores present 0b00 One core core 0 0b01 Two cores core 0 and core 1 0b10 Three cores cores 0 to 2 0b11 Four cores cores 0 to 3 These bits are read only and the value of this field is set to the number of cores present in the configuration 23 Reserved RES0 22 CPU Cache Protection CPU Cache Protection Core RAMs are implemented 0 Without ECC 1 With ECC 21 SCU L2 Cache Protection SCU L2 Cache...

Page 169: ...tended Control Register on page 4 253 There is one copy of this register that is used in both Secure and Non secure states There is one L2ECTLR_EL1 for the Cortex A53 processor Attributes L2ECTLR_EL1 is a 32 bit register Figure 4 59 shows the L2ECTLR_EL1 bit assignments Figure 4 59 L2ECTLR_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 31 0 30 28 RES0 RES0 29 L2 ...

Page 170: ...sible values are 0 No pending asynchronous error This is the reset value 1 An asynchronous error has occurred A write of 0 clears this bit and drives nINTERRIRQ HIGH A write of 1 is ignored 29 AXI or CHI asynchronous error AXI or CHI asynchronous error indication The possible values are 0 No pending asynchronous error 1 An asynchronous error has occurred A write of 0 clears this bit and drives nEX...

Page 171: ...as no outstanding ACP requests to the Cortex A53 processor When the L2 memory system is idle the processor can update the L2ACTLR_EL1 followed by an ISB After the L2ACTLR_EL1 is updated the MMUs can be enabled and normal ACE and ACP traffic can resume Configurations There is one copy of this register that is used in both Secure and Non secure states L2ACTLR_EL1 is mapped to the AArch32 L2ACTLR reg...

Page 172: ...teEvict transactions for UniqueClean evictions with data WriteEvict transactions update downstream caches that are outside the cluster Enable WriteEvict transactions only if there is an L3 or system cache implemented in the system The possible values are 0 Disables UniqueClean evictions with data This is the reset value for ACE 1 Enables UniqueClean evictions with data This is the reset value for ...

Page 173: ... NS See Physical Address Register on page 4 251 Attributes PAR_EL1 is a 64 bit register Figure 4 62 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully Figure 4 62 PAR_EL1 pass bit assignments VA 63 0 Table 4 102 FAR_EL3 bit assignments Bits Name Function 63 0 VA The faulting Virtual Address for all synchronous instruction or data aborts...

Page 174: ...I 0500D Copyright 2013 2014 ARM All rights reserved 4 113 ID021414 Non Confidential Table 4 103 on page 4 114 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully ...

Page 175: ...his value is reserved 0b0100 Device not nGnRnE memory if AttrH is 0b0000 Otherwise Normal memory Inner Non cacheable 0b1000 Reserved if AttrH is 0b0000 Otherwise Normal memory Inner Write Through Cacheable 0b1001 Reserved if AttrH is 0b0000 Otherwise Normal memory Inner Write Through Cacheable Inner Write Allocate 0b1010 Reserved if AttrH is 0b0000 Otherwise Normal memory Inner Write Through Cache...

Page 176: ...ble entry The Possible values are 0b00 Non shareable 0b01 Reserved 0b10 Outer Shareable 0b11 Inner Shareable Note Takes the value of 0b10 for Any type of device memory Normal memory with both Inner Non cacheable and Outer cacheable attributes 6 1 Reserved RES0 0 F Pass Fail bit Indicates whether the conversion completed successfully This value is 0 Virtual Address to Physical Address conversion co...

Page 177: ...n page 4 256 MAIR0 NS when TTBCR EAE is 1 See Memory Attribute Indirection Registers 0 and 1 on page 4 259 Table 4 104 PAR_EL1 fail bit assignments Bits Name Function 63 12 Reserved RES0 11 Reserved RES1 10 Reserved RES0 9 S Stage of fault Indicates the state where the translation aborted The possible values are 0 Translation aborted because of a fault in stage 1 translation 1 Translation aborted ...

Page 178: ...bit assignments Bits Meaning 0b0000 Device memory See Table 4 106 for the type of Device memory 0b00RW RW not 00 Normal Memory Outer Write through transient a a The transient hint is ignored 0b0100 Normal Memory Outer Non Cacheable 0b01RW RW not 00 Normal Memory Outer Write back transient a 0b10RW Normal Memory Outer Write through non transient 0b11RW Normal Memory Outer Write back non transient T...

Page 179: ...e cached in a TLB Configurations MAIR_EL2 31 0 is architecturally mapped to AArch32 register HMAIR0 MAIR_EL2 63 32 is architecturally mapped to AArch32 register HMAIR1 Attributes MAIR_EL2 is a 64 bit register The MAIR_EL2 bit assignments follow the same pattern as described in Figure 4 64 on page 4 117 The description of the MAIR_EL2 bit assignments are the same as described in Table 4 105 on page...

Page 180: ...e as described in Table 4 105 on page 4 117 and Table 4 108 on page 4 120 To access the MAIR_EL3 MRS Xt MAIR_EL3 Read EL3 Memory Attribute Indirection Register MSR MAIR_EL3 Xt Write EL3 Memory Attribute Indirection Register 4 3 72 Vector Base Address Register EL1 The VBAR_EL1 characteristics are Purpose Holds the exception base address for any exception that is taken to EL1 Usage constraints This ...

Page 181: ...Base Address Register on page 4 266 Attributes VBAR_EL2 is a 64 bit register Figure 4 66 shows the VBAR_EL2 bit assignments Figure 4 66 VBAR_EL2 bit assignments Table 4 109 shows the VBAR_EL2 bit assignments To access the VBAR_EL2 MRS Xt VBAR_EL2 Read VBAR_EL2 into Xt MSR VBAR_EL2 Xt Write Xt to VBAR_EL2 Table 4 108 VBAR_EL1 bit assignments Bits Name Function 63 11 Vector base address Base address...

Page 182: ...ssignments Table 4 111 shows the VBAR_EL3 bit assignments To access the VBAR_EL3 MRS Xt VBAR_EL3 Read EL3 Vector Base Address Register MSR VBAR_EL3 Xt Write EL3 Vector Base Address Register 4 3 75 Reset Vector Base Address Register EL3 The RVBAR_EL3 characteristics are Purpose Contains the address that execution starts from after reset when executing in the AArch64 state RVBAR_EL3 is part of the R...

Page 183: ...oots into and allows request of a warm reset Usage constraints This register is accessible as follows Configurations The RMR_EL3 is architecturally mapped to the AArch32 RMR register Attributes RMR_EL3 is a 32 bit register Figure 4 69 on page 4 123 shows the RMR_EL3 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO 0 Reset Vector Base Address 63 Table 4 112 RVBAR_EL3 bit assignm...

Page 184: ... is a 32 bit register Figure 4 70 on page 4 124 shows the ISR_EL1 bit assignments 31 0 RES0 1 2 AA64 RR Table 4 113 RMR_EL3 bit assignments Bits Name Function 31 2 Reserved RES0 1 RR Reset Request The possible values are 0 This is the reset value 1 Requests a warm reset This bit is set to 0 by either a cold or warm reset The bit is strictly a request 0 AA64a Determines which execution state the pr...

Page 185: ...Control Register for each core in the cluster Usage constraints This register is accessible as follows 31 9 8 7 6 5 0 Reserved F I A Reserved Table 4 114 ISR_EL1 bit assignments Bits Name Function 31 9 Reserved RES0 8 A External abort pending bit 0 No pending external abort 1 An external abort is pending 7 I IRQ pending bit Indicates whether an IRQ interrupt is pending 0 No pending IRQ 1 An IRQ in...

Page 186: ...ormance on your code Therefore it is suggested that you do not modify this register unless directed by ARM Configurations CPUACTLR_EL1 is Common to the Secure and Non secure states Mapped to the AArch32 CPUACTLR register CPU Auxiliary Control Register on page 4 269 Attributes CPUACTLR_EL1 is a 64 bit register Figure 4 71 shows the CPUACTLR_EL1 bit assignments Figure 4 71 CPUACTLR_EL1 bit assignmen...

Page 187: ...consecutive streaming cache line does not allocate in the L1 or L2 cache 0b11 Disables streaming All write allocate lines allocate in the L1 or L2 cache 26 25 L1RADIS Write streaming no L1 allocate threshold The possible values are 0b00 4th consecutive streaming cache line does not allocate in the L1 cache This is the reset value 0b01 64th consecutive streaming cache line does not allocate in the ...

Page 188: ...tch streams The possible values are 0 2 linefills to consecutive cache lines triggers prefetch This is the reset value 1 3 linefills to consecutive cache lines triggers prefetch In both configurations Three linefills with a fixed stride pattern are required to trigger prefetch if the stride spans more than one cache line 16 Reserved RES0 15 13 L1PCTL L1 Data prefetch control The value of the this ...

Page 189: ...te accessible in EL1 if ACTLR_EL3 CPUECTLR is 1 and ACTLR_EL2 CPUECTLR is 1 or ACTLR_EL3 CPUECTLR is 1 and SCR NS is 0 The CPUECTLR_EL1 is write accessible in EL2 if ACTLR_EL3 CPUECTLR is 1 Configurations The CPUECTLR_EL1 is Architecturally mapped to the AArch32 CPUECTLR register See CPU Extended Control Register on page 4 271 Attributes CPUECTLR_EL1 is a 64 bit register Figure 4 72 shows the CPUE...

Page 190: ...ion circuit This is the reset value 0b001 2 Architectural Timer ticks are required before retention entry 0b010 8 Architectural Timer ticks are required before retention entry 0b011 32 Architectural Timer ticks are required before retention entry 0b100 64 Architectural Timer ticks are required before retention entry 0b101 128 Architectural Timer ticks are required before retention entry 0b110 256 ...

Page 191: ...here is one copy of this register that is used in both Secure and Non secure states A write of any value to the register updates the register to 0 Attributes CPUMERRSR_EL1 is a a 64 bit register Figure 4 143 on page 4 276 shows the CPUMERRSR_EL1 bit assignments Figure 4 73 CPUMERRSR_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 24 23 21 20 Other error count Repe...

Page 192: ...emented on any memory error that exactly matches the RAMID and Bank Way information in this register while the sticky Valid bit is set The reset value is 0 31 Valid Valid bit This bit is set to 1 on the first memory error It is a sticky bit so that after it is set it remains set until the register is written The reset value is 0 30 24 RAMID RAM Identifier Indicates the RAM in which the first memor...

Page 193: ...15_c2_2 Read CPUMERRSR into Xt MSR S3_1_c15_c2_2 Xt Write Xt to CPUMERRSR 4 3 81 L2 Memory Error Syndrome Register The L2MERRSR_EL1 characteristics are Purpose Holds information about ECC errors on the L2 data RAMs L2 tag RAMs SCU snoop filter RAMs Usage constraints This register is accessible as follows Configurations The L2MERRSR_EL1 is Mapped to the AArch32 L2MERRSR register See L2 Memory Error...

Page 194: ...incremented on any memory error that does not match the RAMID and Bank Way information in this register while the sticky Valid bit is set The reset value is 0 39 32 Repeat error count This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID and Bank Way information in this register while the sticky Valid bit is set The reset value is 0 ...

Page 195: ...se Holds the physical base address of the memory mapped GIC CPU interface registers Usage constraints This register is accessible as follows Configurations There is one copy of this register that is used in both Secure and Non secure states Attributes CBAR_EL1 is a 64 bit register Figure 4 75 shows the CBAR_EL1 bit assignments Figure 4 75 CBAR_EL1 bit assignments Table 4 120 shows the CBAR_EL1 bit...

Page 196: ...sters on page 4 139 c4 registers on page 4 139 c5 registers on page 4 140 c6 registers on page 4 140 c7 registers on page 4 140 c9 registers on page 4 141 c10 registers on page 4 142 c11 registers on page 4 142 c12 registers on page 4 142 c13 registers on page 4 144 c14 registers on page 4 144 c15 registers on page 4 146 The following subsection describes the 64 bit registers and provides cross re...

Page 197: ...this section Table 4 121 System register field values Heading Description CRn System control primary register number Op1 Arguments to the register access instruction CRm Op2 Name The name of the register or operation Some assemblers support aliases that you can use to access the registers and operations by name Reset Reset value of register Description Cross reference to the register description ...

Page 198: ...ature Register 1 on page 4 166 6 ID_MMFR2 0x01260000 Memory Model Feature Register 2 on page 4 168 7 ID_MMFR3 0x02102211 Memory Model Feature Register 3 on page 4 170 c2 0 ID_ISAR0 0x02101110 Instruction Set Attribute Register 0 on page 4 172 1 ID_ISAR1 0x13112111 Instruction Set Attribute Register 1 on page 4 173 2 ID_ISAR2 0x21232042 Instruction Set Attribute Register 2 on page 4 175 3 ID_ISAR3 ...

Page 199: ...rol Register on page 4 202 c3 1 SDCR 0x00000000 Secure Debug Control Register on page 4 204 4 c0 0 HSCTLR 0x03C50838 Hyp System Control Register on page 4 207 1 HACTLR 0x00000000 Auxiliary Control Register EL2 on page 4 55 c1 0 HCR 0x00000000 Hyp Configuration Register on page 4 211 1 HDCR 0x00000006 Hyp Debug Control Register on page 4 217 2 HCPTR 0x000033FFc Hyp Architectural Feature Trap Regist...

Page 200: ...0 UNK Translation Table Base Register 0 on page 4 224 1 TTBR1 UNK Translation Table Base Register 1 on page 4 226 2 TTBCR 0x00000000a Hyp Translation Control Register on page 4 232 4 c0 2 HTCR UNK Hyp Translation Control Register on page 4 232 c1 2 VTCR UNK Virtualization Translation Control Register on page 4 233 a The reset value is 0x00000000 for the Secure copy of the register The reset value ...

Page 201: ...Register on page 4 239 1 IFSR UNK Instruction Fault Status Register on page 4 243 c1 0 ADFSR 0x00000000 Auxiliary Data Fault Status Register on page 4 246 1 AIFSR 0x00000000 Auxiliary Instruction Fault Status Register on page 4 246 c5 4 c1 0 HADFSR 0x00000000 Hyp Auxiliary Data Fault Status Syndrome Register on page 4 246 1 HAIFSR 0x00000000 Hyp Auxiliary Instruction Fault Status Syndrome Register...

Page 202: ...er 5 PMSELR UNK Performance Monitors Event Counter Selection Register 6 PMCEID0 0x67FFBFFFa Performance Monitors Common Event Identification Register 0 on page 12 18 7 PMCEID1 0x00000000 Performance Monitors Common Event Identification Register 1 on page 12 21 c13 0 PMCCNTR UNK Performance Monitors Cycle Counter 1 PMXEVTYPER UNK Performance Monitors Selected Event Type and Filter Register 2 PMXEVC...

Page 203: ...n page 4 263 1 AMAIR1 0x00000000 Auxiliary Memory Attribute Indirection Register 1 on page 4 263 4 c2 0 HMAIR0 UNK Hyp Memory Attribute Indirection Register 0a 1 HMAIR1 UNK Hyp Memory Attribute Indirection Register 1a c3 0 HAMAIR0 0x00000000 Hyp Auxiliary Memory Attribute Indirection Register 0 on page 4 263 1 HAMAIR1 0x00000000 Hyp Auxiliary Memory Attribute Indirection Register 1 on page 4 263 a...

Page 204: ...rrupt Controller Hyp Control Register 1 ICH_VTR 0x90000003 Interrupt Controller VGIC Type Register 2 ICH_MISR 0x00000000 Interrupt Controller Maintenance Interrupt State Register 3 ICH_EISR 0x00000000 Interrupt Controller End of Interrupt Status Register 7 ICH_VMCR 0x004C0000 Interrupt Controller Virtual Machine Control Register 5 ICH_ELSR 0x0000000F Interrupt Controller Empty List Register Status...

Page 205: ... 0x00000000 FCSE Process ID Register on page 4 267 1 CONTEXTIDR UNK Context ID Registera 2 TPIDRURW UNK User Read Write Thread ID Registera 3 TPIDRURO UNK User Read Only Thread ID Registera 4 TPIDRPRW UNK EL1 only Thread ID Registera 4 c0 2 HTPIDR UNK Hyp Software Thread ID Registera a See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile Table 4 134 c14 register summary...

Page 206: ...YPER5 UNK c15 7 PMCCFILTR 0x00000000 Performance Monitor Cycle Count Filter Register 4 c1 0 CNTHCTL c Timer Control Register EL2 c2 0 CNTHP_TVAL UNK Physical Timer TimerValue EL2 1 CNTHP_CTL b Physical Timer Control Register EL2 a The reset value for bits 9 8 2 0 is 0b00000 b The reset value for bit 0 is 0 c The reset value for bit 2 is 0 and for bits 1 0 is 0b11 Table 4 134 c14 register summary c...

Page 207: ... Direct access to internal memory on page 6 13 3 CDBGDR3 UNK Cache Debug Data Register 3 see Direct access to internal memory on page 6 13 c2 0 CDBGDCT UNK Cache Debug Data Cache Tag Read Operation Register see Direct access to internal memory on page 6 13 1 CDBGICT UNK Cache Debug Instruction Cache Tag Read Operation Register see Direct access to internal memory on page 6 13 c4 0 CDBGDCD UNK Cach...

Page 208: ...ble Base Register 6 c2 VTTBR UNK Virtualization Translation Table Base Register 0 c7 PAR UNK Physical Address Register on page 4 251 0 c14 CNTPCT UNK Physical Timer Count Register 1 c14 CNTVCT UNK Virtual Timer Count Register 2 c14 CNTP_CVAL UNK Physical Timer CompareValue Register 3 c14 CNTV_CVAL UNK Virtual Timer CompareValue Register 4 c14 CNTVOFF UNK Virtual Timer Offset Register 6 c14 CNTHP_C...

Page 209: ... ID_MMFR2 6 0x01260000 Memory Model Feature Register 2 on page 4 168 ID_MMFR3 7 0x02102211 Memory Model Feature Register 3 on page 4 170 ID_ISAR0 c2 0 0x02101110 Instruction Set Attribute Register 0 on page 4 172 ID_ISAR1 1 0x13112111 Instruction Set Attribute Register 1 on page 4 173 ID_ISAR2 2 0x21232042 Instruction Set Attribute Register 2 on page 4 175 ID_ISAR3 3 0x01112131 Instruction Set Att...

Page 210: ... Domain Access Control Register on page 4 235 PRRR c10 0 c2 0 UNK 32 bit Primary Region Remap Register on page 4 256 MAIR0 0 UNK 32 bit Memory Attribute Indirection Registers 0 and 1 on page 4 259 NMRR 1 UNK 32 bit Normal Memory Remap Register on page 4 262 MAIR1 1 UNK 32 bit Memory Attribute Indirection Registers 0 and 1 on page 4 259 AMAIR0 c3 0 0x00000000 32 bit Auxiliary Memory Attribute Indir...

Page 211: ...ata Fault Status Register on page 4 239 IFSR 1 UNK Instruction Fault Status Register on page 4 243 ADFSR c1 0 0x00000000 Auxiliary Data Fault Status Register on page 4 246 AIFSR 1 0x00000000 Auxiliary Instruction Fault Status Register on page 4 246 DFAR c6 0 c0 0 UNK Data Fault Address Register see the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile IFAR 2 UNK Instruction ...

Page 212: ...PMCR c9 0 c12 0 0x41033000 Performance Monitors Control Register on page 12 7 PMCNTENSET 1 UNK Performance Monitors Count Enable Set Register PMCNTENCLR 2 UNK Performance Monitors Count Enable Clear Register PMOVSR 3 UNK Performance Monitors Overflow Flag Status Register PMSWINC 4 UNK Performance Monitors Software Increment Register PMSELR 5 UNK Performance Monitors Event Counter Selection Registe...

Page 213: ...VTYPER3 3 UNK PMEVTYPER4 4 UNK PMEVTYPER5 5 UNK PMCCFILTR c15 7 0x00000000 Performance Monitors Cycle Count Filter Register a The reset value is 0x623FFFFF if L2 cache is not implemented Table 4 143 Performance monitor registers continued Name CRn Op1 CRm Op2 Reset Description Table 4 144 Security registers Name CRn Op1 CRm Op2 Reset Description SCR c1 0 c1 0 0x00000000 Secure Configuration Regist...

Page 214: ...trol Register HTTBR 4 c2 UNK 64 bit Hyp Translation Table Base Register VTTBR 6 c2 UNK 64 bit Virtualization Translation Table Base Register HADFSR c5 4 c1 0 0x00000000 32 bit Hyp Auxiliary Data Fault Status Syndrome Register on page 4 246 HAIFSR 1 0x00000000 32 bit Hyp Auxiliary Instruction Fault Status Syndrome Register on page 4 246 HSR c2 0 UNK 32 bit Hyp Syndrome Register on page 4 246 HDFAR ...

Page 215: ... ICC_DIR c11 1 WO 32 bit Deactivate Interrupt Register ICC_RPR 3 RO 32 bit Running Priority Register ICC_IAR1 c12 0 RO 32 bit Interrupt Acknowledge Register 1 ICC_EOIR1 1 WO 32 bit End Of Interrupt Register 1 ICC_HPPIR1 2 RO 32 bit Highest Priority Pending Interrupt Register 1 ICC_BPR1 3 RW 0x00000003a 32 bit Binary Point Register 1 ICC_CTLR 4 RW 0x00000400 32 bit Interrupt Control Register ICC_SR...

Page 216: ...00000000 32 bit Interrupt Controller List Register 2 ICH_LR1 3 RW 0x00000000 32 bit Interrupt Controller List Register 3 ICH_LRC0 c14 0 RW 0x00000000 32 bit Interrupt Controller List Register 0 ICH_LRC1 1 RW 0x00000000 32 bit Interrupt Controller List Register 1 ICH_LRC2 2 RW 0x00000000 32 bit Interrupt Controller List Register 2 ICH_LRC3 3 RW 0x00000000 32 bit Interrupt Controller List Register 3...

Page 217: ...emory on page 6 13 CDBGDCT c2 0 UNK Data Cache Tag Read Operation Register see Direct access to internal memory on page 6 13 CDBGICT 1 UNK Instruction Cache Tag Read Operation Register see Direct access to internal memory on page 6 13 CDBGDCD c4 0 UNK Data Cache Data Read Operation Register see Direct access to internal memory on page 6 13 CDBGICD c4 1 UNK Instruction Cache Data Read Operation Reg...

Page 218: ...s the MIDR bit assignments Figure 4 76 MIDR bit assignments Table 4 148 shows the MIDR bit assignments To access the MIDR EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO Variant Implementer 31 23 20 19 16 15 4 3 0 Architecture PartNum Revision 24 Table 4 148 MIDR bit assignments Bits Name Function 31 24 Implementer Indicates the implementer code This value is 0x41 ASCII char...

Page 219: ...ccessible from the external debug interface Usage constraints This register is accessible as follows Configurations The MPIDR is Architecturally mapped to the AArch64 MPIDR_EL1 31 0 register See Multiprocessor Affinity Register on page 4 15 Architecturally mapped to external EDDEVAFF0 register There is one copy of this register that is used in both Secure and Non secure states Attributes MPIDR is ...

Page 220: ...s 0 Core is part of a cluster 29 25 Reserved RES0 24 MT Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi threading type approach This value is 0 Performance of cores at the lowest affinity level is largely independent 23 16 Aff2 Affinity level 2 Second highest level affinity field Indicates the value read in the CLUSTERIDAFF2 configuration...

Page 221: ...oded as follows 4 5 4 TCM Type Register The processor does not implement the features described by the TCMTR so this register is always RAZ 4 5 5 TLB Type Register The processor does not implement the features described by the TLBTR so this register is always RAZ 4 5 6 Processor Feature Register 0 The ID_PFR0 characteristics are Purpose Gives top level information about the instruction sets suppor...

Page 222: ...coded as follows EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO 31 12 11 8 7 0 RES0 State2 State1 16 15 4 3 State0 State3 Table 4 154 ID_PFR0 bit assignments Bits Name Function 31 16 Reserved RES0 15 12 State3 Indicates support for Thumb Execution Environment T32EE instruction set This value is 0x0 Processor does not support the T32EE instruction set 11 8 State2 Indicates s...

Page 223: ... interpreted with ID_PFR0 Configurations ID_PFR1 is architecturally mapped to AArch64 register ID_PFR1_EL1 See AArch32 Processor Feature Register 1 on page 4 18 There is one copy of this register that is used in both Secure and Non secure states Attributes ID_PFR1 is a 32 bit register Figure 4 80 shows the ID_PFR1 bit assignments Figure 4 80 ID_PFR1 bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL...

Page 224: ...n secure states Table 4 156 ID_PFR1 bit assignments Bits Name Function 31 28 GIC CPU GIC CPU support 0x0 GIC CPU interface is disabled GICCDISABLE is HIGH 0x1 GIC CPU interface is enabled GICCDISABLE is LOW 27 20 Reserved RAZ 19 16 GenTimer Generic Timer support 0x1 Generic Timer implemented 15 12 Virtualization Indicates support for Virtualization 0x1 Virtualization implemented 11 8 MProgMod M pr...

Page 225: ...ance Monitor Unit version 3 PMUv3 system registers 23 20 MProfDbg Indicates support for memory mapped debug model for M profile processors 0x0 Processor does not support M profile Debug architecture 19 16 MMapTrc Indicates support for memory mapped trace model 0x1 Support for ARM trace architecture with memory mapped access In the Trace registers the ETMIDR gives more information about the impleme...

Page 226: ...y Model Feature Register 1 on page 4 166 Memory Model Feature Register 2 on page 4 168 Memory Model Feature Register 3 on page 4 170 Configurations ID_MMFR0 is architecturally mapped to AArch64 register ID_MMFR0_EL1 There is one copy of this register that is used in both Secure and Non secure states Attributes ID_MMFR0 is a 32 bit register Figure 4 82 shows the ID_MMFR0 bit assignments Figure 4 82...

Page 227: ...supported 23 20 AuxReg Indicates support for Auxiliary registers 0x1 Support for Auxiliary Control Register only 19 16 TCM Indicates support for TCMs and associated DMAs 0x0 Not supported 15 12 ShareLvl Indicates the number of shareability levels implemented 0x1 Two levels of shareability implemented 11 8 OuterShr Indicates the outermost shareability domain implemented 0x1 Implemented with hardwar...

Page 228: ... Indicates branch predictor management requirements 0x4 For execution correctness branch predictor requires no flushing at any time 27 24 L1TstCln Indicates the supported L1 Data cache test and clean operations for Harvard or unified cache implementation 0x0 None supported 23 20 L1Uni Indicates the supported entire L1 cache maintenance operations for a unified cache implementation 0x0 None support...

Page 229: ... 0 on page 4 165 Memory Model Feature Register 1 on page 4 166 Memory Model Feature Register 3 on page 4 170 Configurations ID_MMFR2 is architecturally mapped to AArch64 register ID_MMFR2_EL1 There is one copy of this register that is used in both Secure and Non secure states Attributes ID_MMFR2 is a 32 bit register Figure 4 84 shows the ID_MMFR2 bit assignments Figure 4 84 ID_MMFR2 bit assignment...

Page 230: ...tions are Invalidate all entries in the TLB Invalidate TLB entry by MVA Invalidate TLB entries by ASID match Invalidate instruction TLB and data TLB entries by MVA All ASID This is a shared unified TLB operation Invalidate Hyp mode unified TLB entry by MVA Invalidate entire Non secure EL1 and EL0 unified TLB Invalidate entire Hyp mode unified TLB TLBIMVALIS TLBIMVAALIS TLBIMVALHIS TLBIMVAL TLBIMVA...

Page 231: ... 4 172 Memory Model Feature Register 1 on page 4 166 Memory Model Feature Register 2 on page 4 168 Configurations ID_MMFR3 is architecturally mapped to AArch64 register ID_MMFR3_EL1 See AArch32 Memory Model Feature Register 3 on page 4 26 There is one copy of this register that is used in both Secure and Non secure states Attributes ID_MMFR3 is a 32 bit register Figure 4 85 shows the ID_MMFR3 bit ...

Page 232: ...rding to shareability and defined behavior of instructions 11 8 BPMaint Branch predictor maintenance Indicates the supported branch predictor maintenance operations 0x2 Supported branch predictor maintenance operations are Invalidate all branch predictors Invalidate branch predictors by MVA 7 4 CMaintSW Cache maintenance by set way Indicates the supported cache maintenance operations by set way 0x...

Page 233: ...r 2 on page 4 175 Instruction Set Attribute Register 3 on page 4 178 Instruction Set Attribute Register 4 on page 4 179 Instruction Set Attribute Register 5 on page 4 181 Configurations ID_ISAR0 is architecturally mapped to AArch64 register ID_ISAR0_EL1 See AArch32 Instruction Set Attribute Register 0 on page 4 28 There is one copy of this register that is used in both Secure and Non secure states...

Page 234: ...ruction set SDIV and UDIV in the A32 instruction set 23 20 Debug Indicates the implemented Debug instructions 0x1 BKPT 19 16 Coproc Indicates the implemented Coprocessor instructions 0x0 None implemented except for separately attributed by the architecture including CP15 CP14 Advanced SIMD and Floating point 15 12 CmpBranch Indicates the implemented combined Compare and Branch instructions in the ...

Page 235: ...t Attribute Register 4 on page 4 179 Instruction Set Attribute Register 5 on page 4 181 Configurations ID_ISAR1 is architecturally mapped to AArch64 register ID_ISAR1_EL1 See AArch32 Instruction Set Attribute Register 1 on page 4 29 There is one copy of this register that is used in both Secure and Non secure states Attributes ID_ISAR1 is a 32 bit register Figure 4 87 shows the ID_ISAR1 bit assign...

Page 236: ...instructions with long immediates 0x1 The MOVT instruction The MOV instruction encodings with zero extended 16 bit immediates The T32 ADD and SUB instruction encodings with zero extended 12 bit immediates and other ADD ADR and SUB encodings cross referenced by the pseudocode for those encodings 19 16 IfThen Indicates the implemented If Then instructions in the T32 instruction set 0x1 The IT instru...

Page 237: ...bute Register 4 on page 4 179 Instruction Set Attribute Register 5 on page 4 181 Configurations ID_ISAR2 is architecturally mapped to AArch64 register ID_ISAR2_EL1 See AArch32 Instruction Set Attribute Register 2 on page 4 30 There is one copy of this register that is used in both Secure and Non secure states Attributes ID_ISAR2 is a 32 bit register Figure 4 88 shows the ID_ISAR2 bit assignments F...

Page 238: ...instructions The UMAAL instruction 19 16 MultS Indicates the implemented advanced signed Multiply instructions 0x3 The SMULL and SMLAL instructions The SMLABB SMLABT SMLALBB SMLALBT SMLALTB SMLALTT SMLATB SMLATT SMLAWB SMLAWT SMULBB SMULBT SMULTB SMULTT SMULWB SMULWT instructions and the Q bit in the PSRs The SMLAD SMLADX SMLALD SMLALDX SMLSD SMLSDX SMLSLD SMLSLDX SMMLA SMMLAR SMMLS SMMLSR SMMUL S...

Page 239: ...ion Set Attribute Register 2 on page 4 175 Instruction Set Attribute Register 4 on page 4 179 Instruction Set Attribute Register 5 on page 4 181 Configurations ID_ISAR3 is architecturally mapped to AArch64 register ID_ISAR3_EL1 See AArch32 Instruction Set Attribute Register 3 on page 4 33 There is one copy of this register that is used in both Secure and Non secure states Attributes ID_ISAR3 is a ...

Page 240: ...egister to a low register 19 16 TabBranch Indicates the implemented Table Branch instructions in the T32 instruction set 0x1 The TBB and TBH instructions 15 12 SynchPrim Indicates the implemented Synchronization Primitive instructions 0x2 The LDREX and STREX instructions The CLREX LDREXB STREXB and STREXH instructions The LDREXD and STREXD instructions 11 8 SVC Indicates the implemented SVC instru...

Page 241: ...te Register 3 on page 4 178 Instruction Set Attribute Register 5 on page 4 181 Configurations ID_ISAR4 is architecturally mapped to AArch64 register ID_ISAR4_EL1 See AArch32 Instruction Set Attribute Register 4 on page 4 34 There is one copy of this register that is used in both Secure and Non secure states Attributes ID_ISAR4 is a 32 bit register Figure 4 90 shows the ID_ISAR4 bit assignments Fig...

Page 242: ...chronization Primitive instructions 0x0 The LDREX and STREX instructions The CLREX LDREXB LDREXH STREXB and STREXH instructions The LDREXD and STREXD instructions 19 16 Barrier Indicates the supported Barrier instructions in the A32 and T32 instruction sets 0x1 The DMB DSB and ISB barrier instructions 15 12 SMC Indicates the implemented SMC instructions 0x1 The SMC instruction 11 8 Writeback Indic...

Page 243: ... 4 175 Instruction Set Attribute Register 3 on page 4 178 Instruction Set Attribute Register 4 on page 4 179 Configurations ID_ISAR5 is architecturally mapped to AArch64 register ID_ISAR5_EL1 See AArch32 Instruction Set Attribute Register 5 on page 4 36 There is one copy of this register that is used in both Secure and Non secure states Attributes ID_ISAR5 is a 32 bit register Figure 4 91 shows th...

Page 244: ...implemented See the Cortex A53 MPCore Processor Cryptography Extension Technical Reference Manual for more information 11 8 SHA1 Indicates whether SHA1 instructions are implemented in AArch32 state 0x0 Cryptography Extensions are not implemented or are disabled 0x1 SHA1C SHA1P SHA1M SHA1H SHA1SU0 and SHA1SU1 instructions are implemented See the Cortex A53 MPCore Processor Cryptography Extension Te...

Page 245: ...s WB 31 28 27 12 3 0 RA LineSize WT 30 29 13 2 WA NumSets Associativity Table 4 180 CCSIDR bit assignments Bits Name Function 31 WT Indicates support for Write Through 0 Cache level does not support Write Through 30 WB Indicates support for Write Back 0 Cache level does not support Write Back 1 Cache level supports Write Back 29 RA Indicates support for Read Allocation 0 Cache level does not suppo...

Page 246: ...4 181 CCSIDR encodings CSSELR Cache Size Complete register encoding Register bit field encoding WT WB RA WA NumSets Associativity LineSize 0x0 L1 Data cache 8KB 0x7003E01A 0 1 1 1 0x001F 0x003 0x2 16KB 0x7007E01A 0x003F 0x003 0x2 32KB 0x700FE01A 0x007F 0x003 0x2 64KB 0x701FE01A 0x00FF 0x003 0x2 0x1 L1 Instruction cache 8KB 0x2007E00A 0 0 1 0 0x003F 0x001 0x2 16KB 0x200FE00A 0x007F 0x001 0x2 32KB 0...

Page 247: ... the point of unification for the processor 26 24 LoC Indicates the Level of Coherency for the cache hierarchy 0b0001 L2 cache not implemented 0b0010 A clean to the point of coherency operation requires the L1 and L2 caches to be cleaned 23 21 LoUIS Indicates the Level of Unification Inner Shareable for the cache hierarchy 0b001 L2 cache L2 cache is the last level of cache that must be cleaned or ...

Page 248: ...ta cache Usage constraints This register is accessible as follows If the CSSELR level field is programmed to a cache level that is not implemented then a read of CSSELR returns an UNKNOWN value in CSSELR Level Configurations CSSELR NS is architecturally mapped to AArch64 register CSSELR_EL1 See Cache Size Selection Register on page 4 45 There are separate Secure and Non secure copies of this regis...

Page 249: ...itecturally mapped to AArch64 register CTR_EL0 See Cache Type Register on page 4 47 There is one copy of this register that is used in both Secure and Non secure states Attributes CTR is a 32 bit register Figure 4 95 on page 4 189 shows the CTR bit assignments Table 4 185 CSSELR bit assignments Bits Name Function 31 4 Reserved RES0 3 1 Levela a The combination of Level 0b001 and InD 1 is reserved ...

Page 250: ...itten as a result of the eviction of a cache entry that has had a memory location in it modified 0x4 Cache Write Back granule size is 16 words 23 20 ERG Exclusives Reservation Granule Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load Exclusive and Store Exclusive instructions 0x4 Exclusive reservation granule size is 16 words 19 16 Dm...

Page 251: ...0 c0 0 Write Rt to VPIDR Register access is encoded as follows 4 5 26 Virtualization Multiprocessor ID Register The VMPIDR characteristics are Purpose Provides the value of the Virtualization Multiprocessor ID This is the value returned by Non secure EL1 reads of MPIDR Usage constraints This register is accessible as follows EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW 31 0 VPIDR ...

Page 252: ...cteristics are Purpose Provides the top level control of the system including its memory system Usage constraints The SCTLR is accessible as follows Control bits in the SCTLR that are not applicable to a VMSA implementation read as the value that most closely reflects that implementation and ignore writes Some bits in the register are read only These bits relate to non configurable features of an ...

Page 253: ...nd Non secure copies of this register SCTLR has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH Attributes SCTLR is a 32 bit register Figure 4 98 shows the SCTLR bit assignments Figure 4 98 SCTLR bit assignments 31 30 29 28 27 26 25 24 14 13 12 11 3 2 1 0 M I RES0 V C A EE TRE AFE TE 18 21 20 19 UWXN WXN 9 17 16 15 RES1 nTWE RES0 nTWE RES0 8 7...

Page 254: ...remap enabled TEX 2 1 are reassigned for use as bits managed by the operating system The TEX 0 C and B bits are used to describe the memory region attributes with the MMU remap registers 27 26 Reserved RES0 25 EE Exception Endianness bit The value of this bit defines the value of the CPSR E bit on entry to an exception vector including reset This value also indicates the endianness of the translat...

Page 255: ... can remap this base address using the VBAR 1 High exception vectors base address 0xFFFF0000 This base address is never remapped The input VINITHI defines the reset value of the V bit 12 I Instruction cache enable bit This is a global enable bit for instruction caches 0 Instruction caches disabled If SCTLR M is set to 0 instruction accesses from stage 1 of the EL0 EL1 translation regime are to Nor...

Page 256: ...x11xxxxxxxxxxxx Miscellaneous 16 bit instructions 1x100xxxxxxxxxxx ADD Rd PC imm 01001xxxxxxxxxxx LDR Rd PC imm 0100x1xxx1111xxx ADD 4 CMP 3 MOV BX pc BLX pc 010001xx1xxxx111 ADD 4 CMP 3 MOV 6 THEE RES0 5 CP15BEN CP15 barrier enable 0 CP15 barrier operations disabled Their encodings are UNDEFINED 1 CP15 barrier operations enabled 4 3 Reserved RES1 2 C Cache enable This is a global enable bit for d...

Page 257: ...s not implement the ACTLR NS register This register is always RES0 It is mapped to AArch64 register ACTLR_EL1 See Auxiliary Control Register EL1 on page 4 55 ACTLR S is mapped to AArch64 register ACTLR_EL3 See Auxiliary Control Register EL3 on page 4 56 Attributes ACTLR is a 32 bit register Figure 4 99 shows the ACTLR bit assignments Figure 4 99 ACTLR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 ...

Page 258: ...ccessible from a lower exception level This is the reset value 1 The register is write accessible from EL2 5 L2ECTLR access control L2ECTLR write access control The possible values are 0 The register is not write accessible from a lower exception level This is the reset value 1 The register is write accessible from EL2 4 L2CTLR access control L2CTLR write access control The possible values are 0 T...

Page 259: ...oint registers or instructions generates an Undefined Instruction exception This is the reset value 0b01 Access at EL1 only Any attempt to access Advanced SIMD and Floating point registers or instructions from software executing at EL0 generates an Undefined Instruction exception 0b10 Reserved 0b11 Full access If Advanced SIMD and Floating point are not implemented this field is RES0 21 20 cp10a D...

Page 260: ...straints This register is accessible as follows Any read or write to SCR in Secure EL1 state in AArch32 is trapped as an exception to EL3 Configurations The SCR is a Restricted access register that exists only in the Secure state The SCR is mapped to the AArch64 SCR_EL3 register Attributes SCR is a 32 bit register Figure 4 101 shows the SCR bit assignments Figure 4 101 SCR bit assignments b If the...

Page 261: ...mode other than Monitor mode are trapped to Monitor mode as UNDEFINED if the instruction would otherwise cause suspension of execution that is if The event register is not set There is not a pending WFE wakeup event The instruction does not cause another exception 12 TWI Trap WFI instructions The possible values are 0 WFI instructions are not trapped This is the reset value 1 WFI instructions exec...

Page 262: ...truction to Hyp mode takes priority over the value of this bit 6 nET Not Early Termination This bit disables early termination This bit is not implemented RES0 5 AW A bit writable This bit controls whether CPSR A can be modified in Non secure state CPSR A can be modified only in Secure state This is the reset value CPSR A can be modified in any security state 4 FW F bit writable This bit controls ...

Page 263: ...cess Control Register The NSACR characteristics are Purpose Defines the Non secure access permission to CP0 to CP13 Usage constraints This register is accessible as follows EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW 31 0 RES0 SUNIDEN SUIDEN 1 2 Table 4 197 SDER bit assignments Bits Name Function 31 2 Reserved RES0 1 SUNIDEN Secure User Non invasive Debug Enable The possible v...

Page 264: ...Advanced SIMD functionality 0 This bit has no effect on the ability to write CPACR ASEDIS this is the reset value 1 When executing in Non secure state the CPACR ASEDIS bit has a fixed value of 1 and writes to it are ignored If Advanced SIMD and Floating point are not implemented this bit is RES0 14 12 Reserved RES0 11 cp11 Non secure access to CP11 enable 0 Secure access only Any attempt to access...

Page 265: ...istics are Purpose Controls debug and performance monitors functionality in Secure state Usage constraints This register is accessible as follows Configurations SDCR is mapped to AArch64 register MDCR_EL3 Attributes SDCR is a 32 bit register Figure 4 104 shows the SDCR bit assignments Figure 4 104 SDCR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW 31 14 13 0 18 2...

Page 266: ...atchpoint registers from external debugger is permitted This is the reset value 1 Access to breakpoint and watchpoint registers from external debugger is disabled unless overridden by authentication interface 19 18 Reserved RES0 17 SPME Secure performance monitors enable This allows event counting in Secure state 0 Event counting prohibited in Secure state unless overridden by the authentication i...

Page 267: ...ed to the AArch4 ACTLR_EL2 register See Auxiliary Control Register EL2 on page 4 55 Attributes HACTLR is a 32 bit register Figure 4 105 shows the HACTLR bit assignments Figure 4 105 HACTLR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW 31 0 RES0 L2ACTLR access control 1 2 3 4 5 6 7 L2ECTLR access control L2CTLR access control RES0 CPUECTLR access control CPUACTLR acc...

Page 268: ...rite access control The possible values are 0 The register is not write accessible from Non secure EL1 This is the reset value 1 The register is write accessible from Non secure EL1 Write access from Non secure EL1 also requires ACTLR S 5 to be set 4 L2CTLR access control L2CTLR write access control The possible values are 0 The register is not write accessible from Non secure EL1 This is the rese...

Page 269: ...SCTLR_EL2 See System Control Register EL2 on page 4 58 Attributes HSCTLR is a 32 bit register Figure 4 106 shows the HSCTLR bit assignments Figure 4 106 HSCTLR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RES0 RES0 RES1 RES0 M 31 30 29 26 25 24 22 21 20 19 18 13 12 11 7 6 3 2 1 0 TE RES1 EE FI I RES1 C A WXN RES0 RES0 9 RES0 SED 8 ITD RES1 5 4 CP15BEN RES0 27 28 23...

Page 270: ...his bit is not implemented RES0 20 Reserved RES0 19 WXN Write permission implies Execute Never XN This bit can be used to require all memory regions with write permission to be treated as XN 0 Regions with write permission are not forced to XN 1 Regions with write permission are forced to XN The WXN bit is permitted to be cached in a TLB 18 Reserved RES1 17 Reserved RES0 16 Reserved RES1 15 13 Res...

Page 271: ...s is an enable bit for data and unified caches at EL2 0 Data and unified caches disabled at EL2 1 Data and unified caches enabled at EL2 When this bit is 0 all EL2 Normal memory data accesses and all accesses to the EL2 translation tables are Non cacheable If this register is at the highest exception level implemented field resets to 0 Otherwise its reset value is UNKNOWN 1 A Alignment check enabl...

Page 272: ...0 See Hypervisor Configuration Register on page 4 60 Attributes HCR is a 32 bit register Figure 4 107 shows the HCR bit assignments Figure 4 107 HCR bit assignments 0 M MMU enable This is a global enable bit for the EL2 stage 1 MMU 0 EL2 stage 1 MMU disabled 1 EL2 stage 1 MMU enabled If this register is at the highest exception level implemented field resets to 0 Otherwise its reset value is UNKNO...

Page 273: ...SystemControl ARM DDI 0500D Copyright 2013 2014 ARM All rights reserved 4 212 ID021414 Non Confidential Table 4 202 on page 4 213 shows the HCR bit assignments ...

Page 274: ...SA TDA bits are ignored and the processor behaves as if they are set to 1 other than for the value read back from HDCR The reset value is 0 26 TVM Trap Virtual Memory controls When 1 this causes Writes to the EL1 virtual memory control registers from EL1 to be trapped to EL2 This covers the following registers SCTLR TTBR0 TTBR1 TTBCR DACR DFSR IFSR DFAR IFAR ADFSR AIFSR PRRR MAIR0 NMRR MAIR1 AMAIR...

Page 275: ...to EL2 ID_PFR0 ID_PFR1 ID_DFR0 ID_AFR0 ID_MMFR0 ID_MMFR1 ID_MMFR2 ID_MMFR3 ID_ISAR0 ID_ISAR1 ID_ISAR2 ID_ISAR3 ID_ISAR4 ID_ISAR5 MVFR0 MVFR1 and MVFR2 Also MRC instructions to any of the following encodings CP15 OPC1 is 0 CRn is 0 CRm is c3 c4 c5 c6 or c7 and Opc2 is 0 or 1 CP15 Opc1 is 0 CRn is 0 CRm is c3 and Opc2 is 2 CP15 Opc1 is 0 CRn is 0 CRm is 5 and Opc2 is 4 or 5 The reset value is 0 17 T...

Page 276: ... 1 translation is Normal Non shareable Inner Write Back Write Allocate Outer Write Back Write Allocate The reset value is 0 11 10 BSU Barrier Shareability upgrade The value in this field determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0 The possible values are 0b00 No effect 0b01 Inner Shareable 0b10 Outer Shareable 0b11 Full System The reset value ...

Page 277: ...he FMO bit is set to 1 setting this bit signals a virtual FIQ exception to the Guest OS when the processor is executing in Non secure state at EL0 or EL1 The Guest OS cannot distinguish the virtual exception from the corresponding physical exception The reset value is 0 5 AMO Asynchronous Abort Mask Override When this is set to 1 it overrides the effect of CPSR A and enables virtual exception sign...

Page 278: ...CR NS 0 RW RW RES0 31 0 CD ID 1 2 Table 4 203 HCR2 bit assignments Bits Name Function 31 2 Reserved RES0 1 ID Stage 2 Instruction cache disable When HCR VM is 1 this forces all stage 2 translations for instruction accesses to Normal memory to be Non cacheable for the EL1 EL0 translation regime The possible values are 0 No effect on the stage 2 of the EL1 EL0 translation regime for instruction acce...

Page 279: ...chitecturally mapped to AArch64 register MDCR_EL2 See Hyp Debug Control Register on page 4 66 This register is accessible only at EL2 or EL3 Attributes HDCR is a 32 bit register Figure 4 109 shows the HDCR bit assignments Figure 4 109 HDCR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW 31 11 10 9 8 7 6 5 4 0 RES0 HPMN TDOSA TDA TDE HPME TPM TPMCR 12 TDRA ...

Page 280: ...SystemControl ARM DDI 0500D Copyright 2013 2014 ARM All rights reserved 4 219 ID021414 Non Confidential Table 4 204 on page 4 220 shows the HDCR bit assignments ...

Page 281: ...and treated as though it is 1 other than for the value read back from HDCR On Warm reset the field resets to 0 9 TDA Trap Debug Access 0 Has no effect on accesses to CP14 Debug registers 1 Trap valid Non secure accesses to CP14 Debug registers to Hyp mode When this bit is set to 1 any valid access to the CP14 Debug registers other than the registers trapped by the TDRA and TDOSA bits is trapped to...

Page 282: ... more information 4 0 HPMN Hyp Performance Monitor count Defines the number of Performance Monitors counters that are accessible from Non secure EL1 and EL0 modes if unprivileged access is enabled In Non secure state HPMN divides the Performance Monitors counters as follows If software is accessing Performance Monitors counter n then in Non secure state For example If PMnEVCNTR is performance moni...

Page 283: ... the HCPTR behaves as RAO WI for Non secure accesses See the bit description for TASE Configurations HCPTR is architecturally mapped to AArch64 register CPTR_EL2 Attributes HCPTR is a 32 bit register Figure 4 110 shows the HCPTR bit assignments Figure 4 110 HCPTR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RES0 31 30 21 20 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 284: ...n Non secure accesses to the HCPTR the TASE bit behaves as RAO WI 14 12 Reserved RES0 11 TCP11a Trap CP11 The possible values of each of this bit is 0 If NSACR cp11 is set to 1 then Hyp mode can access CP11 regardless of the value of CPACR cp11 This bit value has no effect on possible use of CP11 from Non secure EL1 and EL0 modes 1 Trap valid Non secure accesses to CP11 to Hyp mode Any otherwise v...

Page 285: ...ister 0 EL1 on page 4 79 TTBR0 S is mapped to AArch64 register TTBR0_EL3 See Translation Table Base Register 0 EL3 on page 4 93 There are separate Secure and Non secure copies of this register TTBR0 has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH Attributes TTBR0 is A 32 bit register when TTBCR EAE is 0 A 64 bit register when TTBCR EAE is ...

Page 286: ...NOS Not Outer Shareable bit Indicates the Outer Shareable attribute for the memory associated with a translation table walk that has the Shareable attribute indicated by TTBR0 S is 1 The possible values are 0 Outer Shareable 1 Inner Shareable This bit is ignored when TTBR0 S is 0 4 3 RGN Region bits Indicates the Outer cacheability attributes for the memory associated with the translation table wa...

Page 287: ...n secure copies of this register Attributes TTBR1 is A 32 bit register when TTBCR EAE is 0 A 64 bit register when TTBCR EAE is 1 There are two formats for this register TTBCR EAE determines which format of the register is used This section describes TTBR1 format when using the Short descriptor translation table format on page 4 227 TTBR1 format when using the Long descriptor translation table form...

Page 288: ...lation Table Base Address Its effects are CONSTRAINED UNPREDICTABLE where bits x 1 7 are treated as if all the bits are zero The value read back from those bits is the value written 6 Reserved RES0 5 NOS Not Outer Shareable bit Indicates the Outer Shareable attribute for the memory associated with a translation table walk that has the Shareable attribute indicated by TTBR0 S is 1 The possible valu...

Page 289: ...CR 30 when using the Long descriptor translation table format so this bit is RES0 Configurations TTBCR NS is architecturally mapped to AArch64 register TCR_EL1 See Translation Control Register EL1 on page 4 86 There are separate Secure and Non secure copies of this register BADDR 47 x 47 48 0 63 ASID RES0 55 56 Table 4 209 TTBR1 bit assignments TTBCR EAE is 1 Bits Name Function 63 56 Reserved RES0...

Page 290: ...ort descriptor translation table format 30 6 Reserved RES0 5 PD1 Translation table walk disable for translations using TTBR1 This bit controls whether a translation table walk is performed on a TLB miss for an address that is translated using TTBR1 The possible values are 0 Perform translation table walks using TTBR1 1 A TLB miss on an address that is translated using TTBR1 generates a Translation...

Page 291: ...lity attribute for memory associated with translation table walks using TTBR1 0b00 Normal memory Outer Non cacheable 0b01 Normal memory Outer Write Back Write Allocate Cacheable 0b10 Normal memory Outer Write Through Cacheable 0b11 Normal memory Outer Write Back no Write Allocate Cacheable Resets to 0 25 24 IRGN1 Inner cacheability attribute for memory associated with translation table walks using...

Page 292: ...rite Allocate Cacheable 0b10 Normal memory Outer Write Through Cacheable 0b11 Normal memory Outer Write Back no Write Allocate Cacheable Resets to 0 9 8 IRGN0 Inner cacheability attribute for memory associated with translation table walks using TTBR0 0b00 Normal memory Inner Non cacheable 0b01 Normal memory Inner Write Back Write Allocate Cacheable 0b10 Normal memory Inner Write Through Cacheable ...

Page 293: ...eability and shareability information for the accesses Usage constraints This register is accessible as follows Configurations HTCR is architecturally mapped to AArch64 register TCR_EL2 See Translation Control Register EL2 on page 4 89 Attributes HTCR is a 32 bit register Figure 4 117 shows the HTCR bit assignments Figure 4 117 HTCR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SC...

Page 294: ...attribute for memory associated with translation table walks using TTBR0 The possible values are 0b00 Non shareable 0b01 Reserved 0b10 Outer shareable 0b11 Inner shareable 11 10 ORGN0 Outer cacheability attribute for memory associated with translation table walks using TTBR0 The possible values are 0b00 Normal memory Outer Non cacheable 0b01 Normal memory Outer Write Back Write Allocate Cacheable ...

Page 295: ...eable 0b11 Inner Shareable 11 10 ORGN0 Outer cacheability attribute for memory associated with translation table walks using TTBR0 0b00 Normal memory Outer Non cacheable 0b01 Normal memory Outer Write Back Write Allocate Cacheable 0b10 Normal memory Outer Write Through Cacheable 0b11 Normal memory Outer Write Back no Write Allocate Cacheable 9 8 IRGN0 Inner cacheability attribute for memory associ...

Page 296: ...select the Long descriptor translation table format Attributes DACR is a 32 bit register Figure 4 119 shows the DACR bit assignments Figure 4 119 DACR bit assignments Table 4 214 shows the DACR bit assignments To access the DACR MRC p15 0 Rt c3 c0 0 Read DACR into Rt MCR p15 0 Rt c3 c0 0 Write Rt to DACR EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 31 30 29 28 27 26 25 24...

Page 297: ...s c0 c3 c5 c13 c15 Usage constraints This register is accessible as follows Configurations HSTR is architecturally mapped to AArch64 register HSTR_EL2 This register is accessible only at EL2 or EL3 Attributes HSTR is a 32 bit register Figure 4 120 shows the HSTR bit assignments Figure 4 120 HSTR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW 31 0 RES0 1 2 3 4 5 6 7 8...

Page 298: ...ccesses to CP15 registers 1 Trap valid Non secure accesses to coprocessor primary register CRn 13 to Hyp mode The reset value is 0 12 T12 Trap coprocessor primary register CRn 12 The possible values are 0 Has no effect on Non secure accesses to CP15 registers 1 Trap valid Non secure accesses to coprocessor primary register CRn 12 to Hyp mode The reset value is 0 11 T11 Trap coprocessor primary reg...

Page 299: ...egister CRn 6 to Hyp mode The reset value is 0 5 T5 Trap coprocessor primary register CRn 5 The possible values are 0 Has no effect on Non secure accesses to CP15 registers 1 Trap valid Non secure accesses to coprocessor primary register CRn 5 to Hyp mode The reset value is 0 4 Reserved RES0 3 T3 Trap coprocessor primary register CRn 3 The possible values are 0 Has no effect on Non secure accesses...

Page 300: ...of this register There are two formats for this register The current translation table format determines which format of the register is used Attributes DFSR is a 32 bit register This section describes DFSR when using the Short descriptor translation table format DFSR when using the Long descriptor translation table format on page 4 241 DFSR when using the Short descriptor translation table format...

Page 301: ... the Fault Status field See bits 3 0 in this table 9 RAZ 8 Reserved RES0 7 4 Domain Specifies which of the 16 domains D15 D0 was being accessed when a data fault occurred For permission faults that generate Data Abort exception this field is UNKNOWN ARMv8 deprecates any use of the domain field in the DFSR 3 0 FS 3 0 Fault Status bits This field indicates the type of exception generated Any encodin...

Page 302: ...l DFSR when using the Long descriptor translation table format Figure 4 122 shows the DFSR bit assignments when using the Long descriptor translation table format Figure 4 122 DFSR bit assignments for Long descriptor translation table format 31 14 13 12 11 10 9 8 5 0 RES0 1 CM ExT WnR RES0 Status 6 RES0 ...

Page 303: ... a write or a read access 0 Abort caused by a read access 1 Abort caused by a write access For faults on CP15 cache maintenance operations including the VA to PA translation operations this bit always returns a value of 1 10 Reserved RES0 9 RAO 8 6 Reserved RES0 5 0 Status Fault Status bits This field indicates the type of exception generated Any encoding not listed is reserved 0b000000 Address si...

Page 304: ... and Non secure copies of this register Attributes IFSR is a 32 bit register There are two formats for this register The current translation table format determines which format of the register is used This section describes IFSR when using the Short descriptor translation table format IFSR when using the Long descriptor translation table format on page 4 244 IFSR when using the Short descriptor t...

Page 305: ...always returns 0 11 Reserved RES0 10 FS 4 Part of the Fault Status field See bits 3 0 in this table 9 RAZ 8 5 Reserved RES0 4 0 FS 3 0 Fault Status bits This field indicates the type of exception generated Any encoding not listed is reserved 0b00010 Debug event 0b00011 Access flag fault section 0b00101 Translation fault section 0b00110 Access flag fault page 0b00111 Translation fault page 0b01000 ...

Page 306: ...2 ExT External abort type This field indicates whether an AXI Decode or Slave error caused an abort 0 External abort marked as DECERR 1 External abort marked as SLVERR For aborts other than external aborts this bit always returns 0 11 10 Reserved RES0 9 RAO 8 6 Reserved RES0 5 0 Status Fault Status bits This field indicates the type of exception generated Any encoding not listed is reserved 0b0000...

Page 307: ...ion Fault Status Syndrome Register The processor does not implement HAIFSR so this register is always RES0 4 5 54 Hyp Syndrome Register The HSR characteristics are Purpose Holds syndrome information for an exception taken to Hyp mode Usage constraints This register is accessible as follows Configurations HSR is architecturally mapped to AArch64 register ESR_EL2 See Exception Syndrome Register EL2 ...

Page 308: ...Holds the virtual address of the faulting address that caused a synchronous Data Abort exception Usage constraints This register is accessible as follows Configurations DFAR NS is architecturally mapped to AArch64 register FAR_EL1 31 0 See Fault Address Register EL1 on page 4 103 DFAR S is architecturally mapped to AArch32 register HDFAR See Hyp Data Fault Address Register on page 4 249 Table 4 22...

Page 309: ...tch Abort exception Usage constraints This register is accessible as follows Configurations IFAR NS is architecturally mapped to AArch64 register FAR_EL1 63 32 See Fault Address Register EL1 on page 4 103 IFAR S is architecturally mapped to AArch32 register HIFAR IFAR S is architecturally mapped to AArch64 register FAR_EL2 63 32 See Fault Address Register EL2 on page 4 104 Attributes IFAR is a 32 ...

Page 310: ...egister FAR_EL2 31 0 when EL3 is AArch64 See Fault Address Register EL2 on page 4 104 HDFAR S is architecturally mapped to AArch32 register DFAR S See Data Fault Address Register on page 4 247 Attributes HDFAR is a 32 bit register Figure 4 128 shows the HDFAR bit assignments Figure 4 128 HDFAR bit assignments on page 4 104Table 4 226 shows the HDFAR bit assignments To access the HDFAR MRC p15 4 Rt...

Page 311: ...tecturally mapped to AArch32 register IFAR S See Instruction Fault Address Register on page 4 248 Attributes HIFAR is a 32 bit register Figure 4 129 shows the HIFAR bit assignments Figure 4 129 HIFAR bit assignments Table 4 227 shows the HIFAR bit assignments To access the HIFAR MRC p15 4 Rt c6 c0 2 Read HIFAR into Rt MCR p15 4 Rt c6 c0 2 Write Rt to HIFAR 4 5 59 Hyp IPA Fault Address Register The...

Page 312: ...hows the HPFAR bit assignments To access the HPFAR MRC p15 4 Rt c6 c0 4 Read HPFAR into Rt MCR p15 4 Rt c6 c0 4 Write Rt to HPFAR 4 5 60 Physical Address Register The processor does not use any implementation defined bits in the 32 bit format or 64 bit format PAR Bit 8 is RES0 See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for more information 4 5 61 L2 Control Re...

Page 313: ...ol Register on page 4 106 There is one L2CTLR for the Cortex A53 processor There is one copy of this register that is used in both Secure and Non secure states Attributes L2CTLR is a 32 bit register Figure 4 131 shows the L2CTLR bit assignments Figure 4 131 L2CTLR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 31 0 26 25 24 Reserved Number of cores RES0 23 1...

Page 314: ... One core core 0 0b01 Two cores core 0 and core 1 0b10 Three cores cores 0 to 2 0b11 Four cores cores 0 to 3 These bits are read only and the value of this field is set to the number of cores present in the configuration 23 Reserved RAZ 22 CPU Cache Protection CPU Cache Protection Core RAMs are implemented 0 without ECC 1 with ECC 21 SCU L2 Cache Protection SCU L2 Cache Protection L2 cache is impl...

Page 315: ...tended Control Register on page 4 107 There is one copy of this register that is used in both Secure and Non secure states There is one L2ECTLR for the Cortex A53 processor Attributes L2ECTLR is a 32 bit register Figure 4 132 shows the L2ECTLR bit assignments Figure 4 132 L2ECTLR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 31 0 30 28 RES0 RES0 29 L2 inter...

Page 316: ...I or CHI asynchronous error AXI or CHI asynchronous error indication The possible values are 0 No pending asynchronous error 1 An asynchronous error has occurred A write of 0 clears this bit A write of 1 is ignored 28 3 Reserved RES0 2 0 L2 dynamic retention control L2 dynamic retention control The possible values are 0b000 L2 dynamic retention disabled This is the reset value 0b001 2 Generic Time...

Page 317: ...chitecturally mapped to AArch64 register MAIR_EL1 31 0 when TTBCR EAE is 0 PRRR S is mapped to AArch64 register MAIR_EL3 31 0 when TTBCR EAE is 0 There are separate Secure and Non secure copies of this register PRRR has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH Attributes PRRR is a 32 bit register when TTBCR EAE 0 Figure 4 133 shows the ...

Page 318: ... Mapping of S 0 attribute for Normal memory This bit gives the mapped Shareable attribute for a region of memory that Is mapped as Normal memory Has the S bit set to 0 The possible values of the bit are the same as those given for the NS1 bit bit 19 17 DS1 Mapping of S 1 attribute for Device memory This bit gives the mapped Shareable attribute for a region of memory that Is mapped as Device memory...

Page 319: ...anslations use Long descriptor translation table formats and MAIR0 replaces the PRRR and MAIR1 replaces the NMRR For more information see Memory Attribute Indirection Registers 0 and 1 on page 4 259 To access the PRRR MRC p15 0 Rt c10 c2 0 Read PRRR into Rt MCR p15 0 Rt c10 c2 0 Write Rt to PRRR Table 4 232 Memory attributes and the n value for the PRRR field descriptions Attributes n value TEX 0 ...

Page 320: ...cure copy of the register gives the value for memory accesses from Secure state The Non secure copy of the register gives the value for memory accesses from Non secure states other than Hyp mode Configurations MAIR0 NS is architecturally mapped to AArch64 register MAIR_EL1 31 0 when TTBCR EAE 1 See Memory Attribute Indirection Register EL1 on page 4 116 MAIR0 S is mapped to AArch64 register MAIR_E...

Page 321: ...the type of Device memory 0b00RW RW not 00 Normal Memory Outer Write through transient a a The transient hint is ignored 0b0100 Normal Memory Outer Non Cacheable 0b01RW RW not 00 Normal Memory Outer Write back transient a 0b10RW Normal Memory Outer Write through non transient 0b11RW Normal Memory Outer Write back non transient Table 4 235 Attr n 3 0 bit assignments Bits Meaning when Attr n 7 4 is ...

Page 322: ...234 on page 4 260and Table 4 235 on page 4 260 to define the read allocate and write allocate policies To access the MAIR0 MRC p15 0 Rt c10 c2 0 Read MAIR0 into Rt MCR p15 0 Rt c10 c2 0 Write Rt to MAIR0 To access the MAIR1 MRC p15 0 Rt c10 c2 1 Read MAIR1 into Rt MCR p15 0 Rt c10 c2 1 Write Rt to MAIR1 Table 4 236 Encoding of R and W bits in some Attrm fields R or W Meaning 0 Do not allocate 1 Al...

Page 323: ...on secure NMRR is architecturally mapped to the AArch64 MAIR_EL1 63 32 register when TTBCR EAE 0 The Secure NMRR is mapped to the AArch64 MAIR_EL3 63 32 register when TTBCR EAE 0 NMRR has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH NMRR has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HI...

Page 324: ...pose Holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode when high exception vectors are not selected Usage constraints This register is accessible as follows Table 4 237 NMRR bit assignments Bits Name Description 2n 17 2n 16 a ORn Outer Cacheable property mapping for memory attributes n if the region is mapped as Normal memory by the PRRR TRn entry n ...

Page 325: ... See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for more information To access the VBAR MRC p15 0 Rt c12 c0 0 Read VBAR into Rt MCR p15 0 Rt c12 c0 0 Write Rt to VBAR 4 5 71 Reset Management Register The RMR characteristics are Purpose Controls the execution state that the processor boots into and allows request of a warm reset Usage constraints This register is a...

Page 326: ...gister Figure 4 137 on page 4 266 shows the ISR bit assignments Table 4 238 RMR bit assignments Bits Name Function 31 2 Reserved RES0 1 RR Reset Request The possible values are 0 This is the reset value 1 Requests a warm reset This bit is set to 0 by either a cold or warm reset The bit is strictly a request The RR bit drives the WARMRSTREQ output signal 0 AA64a Determines which execution state the...

Page 327: ...ions The HVBAR is Architecturally mapped to the AArch64 VBAR_EL2 31 0 See Vector Base Address Register EL2 on page 4 120 31 9 8 7 6 5 0 RES0 F I A RES0 Table 4 240 ISR bit assignments Bits Name Function 31 9 Reserved RES0 8 A External abort pending bit 0 No pending external abort 1 An external abort is pending 7 I IRQ pending bit Indicates whether an IRQ interrupt is pending 0 No pending IRQ 1 An ...

Page 328: ...r only when the L2 memory system is idle ARM recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE CHI or ACP traffic has begun If the register must be modified after a powerup reset sequence to idle the L2 memory system you must take the following steps 1 Disable the MMU from each core followed by an ISB to ensure the MMU disable operation i...

Page 329: ... L2ACTLR MRC p15 1 Rt c15 c0 0 Read L2ACTLR into Rt MCR p15 1 Rt c15 c0 0 Write Rt to L2ACTLR 31 30 29 15 14 13 4 3 2 0 RES0 RES0 Disable clean evict push to external Enable UniqueClean evictions with data L2 Victim Control RES0 Table 4 243 L2ACTLR bit assignments Bits Name Function 31 30 L2 victim Control 0b10 This is the default value Software must not change it 29 15 Reserved RES0 14 Enable Uni...

Page 330: ...enabled and before any ACE or ACP traffic begins Note Setting many of these bits can cause significantly lower performance on your code Therefore it is suggested that you do not modify this register unless directed by ARM Configurations CPUACTLR is Common to the Secure and Non secure states Mapped to the AArch64 CPUACTLR_EL1 register See CPU Auxiliary Control Register EL1 on page 4 124 Attributes ...

Page 331: ...ecutive streaming cache line does not allocate in the L1 or L2 cache 0b11 Disables streaming All write allocate lines allocate in the L1 or L2 cache 26 25 L1RADIS Write streaming no L1 allocate threshold The possible values are 0b00 4th consecutive streaming cache line does not allocate in the L1 cache This is the reset value 0b01 64th consecutive streaming cache line does not allocate in the L1 c...

Page 332: ...split throttle The possible values are 0 Device split throttle disabled 1 Device split throttle enabled This is the reset value 17 STRIDE Enable stride detection The possible values are 0 2 consecutive strides to trigger prefetch This is the reset value 1 3 consecutive strides to trigger prefetch 16 Reserved RES0 15 13 L1PCTL L1 Data prefetch control The value of the this field determines the maxi...

Page 333: ...ions The CPUECTLR is Architecturally mapped to the AArch64 CPUECTLR_EL1 register See CPU Extended Control Register EL1 on page 4 128 Attributes CPUECTLR is a 64 bit register Figure 4 141 shows the CPUECTLR bit assignments Figure 4 141 CPUECTLR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 7 6 5 3 2 RES0 0 63 SMPEN Advanced SIMD FP retention control CPU rete...

Page 334: ... the reset value 0b001 2 Architectural Timer ticks are required before retention entry 0b010 8 Architectural Timer ticks are required before retention entry 0b011 32 Architectural Timer ticks are required before retention entry 0b100 64 Architectural Timer ticks are required before retention entry 0b101 128 Architectural Timer ticks are required before retention entry 0b110 256 Architectural Timer...

Page 335: ...There is one copy of this register that is used in both Secure and Non secure states A write of any value to the register updates the register to 0 Attributes CPUMERRSR is a a 64 bit register Figure 4 143 on page 4 276 shows the CPUMERRSR bit assignments Figure 4 142 CPUMERRSR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW 24 23 21 20 Other error count Repea...

Page 336: ... memory error that exactly matches the RAMID and Bank Way information in this register while the sticky Valid bit is set The reset value is 0 31 Valid Valid bit This bit is set to 1 on the first memory error It is a sticky bit so that after it is set it remains set until the register is written The reset value is 0 30 24 RAMID RAM Identifier Indicates the RAM in which the first memory error The po...

Page 337: ... Read CPUMERRSR into Rt and Rt2 MCRR p15 2 Rt Rt2 c15 Write Rt and Rt2 to CPUMERRSR 4 5 79 L2 Memory Error Syndrome Register The L2MERRSR characteristics are Purpose Holds ECC errors on the L2 data RAMs L2 tag RAMs SCU snoop filter RAMs Usage constraints This register is accessible as follows Configurations The L2MERRSR is Architecturally mapped to the AArch64 L2MERRSR_EL1 register See L2 Memory E...

Page 338: ...emented on any memory error that does not match the RAMID and Bank Way information in this register while the sticky Valid bit is set The reset value is 0 39 32 Repeat error count This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID and Bank Way information in this register while the sticky Valid bit is set The reset value is 0 31 V...

Page 339: ... physical base address of the memory mapped GIC CPU interface registers Usage constraints This register is accessible as follows Configurations The CBAR is Common to the Secure and Non secure states Attributes CBAR is a 32 bit register Figure 4 144 shows the CBAR bit assignments Figure 4 144 CBAR bit assignments Table 4 248 shows the CBAR bit assignments To access the CBAR MRC p15 1 Rt c15 c3 0 Re...

Page 340: ...1 ID021414 Non Confidential Chapter 5 Memory Management Unit This chapter describes the Memory Management Unit MMU It contains the following sections About the MMU on page 5 2 TLB organization on page 5 3 TLB match process on page 5 4 External aborts on page 5 5 ...

Page 341: ...e translation granule is limited to be 4KB A 16 bit ASID In AArch32 the ASID is limited to an 8 bit value The maximum supported physical address size is 40 bits You can enable or disable each stage of the address translation independently The MMU controls table walk hardware that accesses translation tables in main memory The MMU translates virtual addresses to physical addresses The MMU provides ...

Page 342: ...iate block for the lookup stored Accesses to the main TLB take a variable number of cycles based on Competing requests from each of the micro TLBs The TLB maintenance operations in flight The different page size mappings in use 5 2 3 IPA cache RAM The Intermediate Physical Address IPA cache RAM holds mappings between intermediate physical addresses and physical addresses Only Non secure EL1 and EL...

Page 343: ...ds whether the request occurred at the EL3 exception level if EL3 is AArch64 Non secure EL2 exception level Secure and Non secure EL0 or EL1 exception levels and EL3 exception level when EL3 is AArch32 A TLB entry match occurs when the following conditions are met Its VA moderated by the page size such as the VA bits 47 N where N is log2 of the block size for that translation stored in the TLB ent...

Page 344: ... generated because of an uncorrected ECC error in the L1 Data cache or L2 cache arrays See Secure Configuration Register on page 4 76 Secure Configuration Register on page 4 199 or the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for more information 5 4 1 External aborts on data read or write Externally generated aborts during a data read or write can be asynchronous F...

Page 345: ...apter describes the L1 memory system It contains the following sections About the L1 memory system on page 6 2 Cache behavior on page 6 3 Support for v8 memory types on page 6 6 L1 Instruction memory system on page 6 7 L1 Data memory system on page 6 9 Data prefetching on page 6 12 Direct access to internal memory on page 6 13 ...

Page 346: ...cache 128 bit read interface to the L2 memory system The L1 Data memory system has the following features Data side cache line length of 64 bytes 4 way set associative L1 Data cache 256 bit write interface to the L2 memory system 128 bit read interface to the L2 memory system Read buffer that services the Data Cache Unit DCU the Instruction Fetch Unit IFU and the TLB 64 bit read path from the data...

Page 347: ... is no guarantee that they are executed A branch or exceptional instruction in the code stream can cause a pipeline flush discarding the currently fetched instructions Because of the aggressive prefetching behavior you must not place read sensitive devices in the same page as code Pages with Device memory type attributes are treated as Non Cacheable Normal Memory You must mark pages that contain r...

Page 348: ...ns where allocating on writes is not wanted such as executing the C standard library memset function to clear a large block of memory to a known value Writing large blocks of data like this can pollute the cache with unnecessary data It can also waste power and performance if a linefill must be performed only to discard the linefill data because the entire line was subsequently written by the mems...

Page 349: ...s the L2 read allocate mode threshold See CPU Auxiliary Control Register EL1 on page 4 124 In AArch32 CPUACTLR L1RADIS configures the L1 read allocate mode threshold and CPUACTLR RADIS configures the L2 read allocate mode threshold See CPU Auxiliary Control Register on page 4 269 Data cache invalidate on reset The ARMv8 A architecture does not support an operation to invalidate the entire data cac...

Page 350: ...s the ARMv8 memory types As defined by the architecture these bits apply only when the translation table is marked as ARMv8 Device memory they do not apply to Normal memory If an ARMv7 architecture operating system runs on a Cortex A53 processor the Device memory type matches the nGnRE encoding and the Strongly Ordered memory type matches the nGnRnE memory type Table 6 1 ARMv8 memory types Memory ...

Page 351: ...e the flow prediction hardware predicts all branch instructions regardless of the addressing mode including Conditional branches Unconditional branches Indirect branches associated with procedure call and return instructions Branches that switch between A32 and T32 states However some branch instructions are not predicted Data processing instructions using the PC as a destination register The BXJ ...

Page 352: ... Non Confidential LDR pc r13 imm LDM r13 pc LDM r13 pc In AArch64 state the RET instruction causes a return stack pop Because return from exception instructions can change processor privilege mode and security state they are not predicted This includes LDM exception return RFE SUBS pc lr ERET ...

Page 353: ...o HIGH indicates that exclusive accesses are not supported at the address of the transaction and causes a Data Abort exception to be taken with a Data Fault Status Code of 0b110101 when using the long descriptor format 0b10101 when using the short descriptor format A Load Exclusive instruction causes ARLOCKM for ACE or Excl for CHI to be set to HIGH if the memory attributes are Device Inner Non ca...

Page 354: ...Snoop and ARLOCKM set to HIGH WriteNoSnoop and AWLOCKM set to HIGH Inner shared Outer shared Normal inner Non cacheable outer Write Back or Write Through or Normal inner Write Through outer Write Back Write Through or Non cacheable or Normal inner Write Back outer Non cacheable or Write Through Non shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop ReadNoSnoop Inner shared System ReadNoSnoop Write...

Page 355: ...red Outer shared Normal inner Non cacheable outer Write Back or Write Through or Normal inner Write Through outer Write Back Write Through or Non cacheable or Normal inner Write Back outer Non cacheable or Write Through Non shared Non snoopable ReadNoSnp WriteNoSnp ReadNoSnp ReadNoSnp Inner shared Non snoopable ReadNoSnp WriteNoSnp ReadNoSnp with Excl set to HIGH WriteNoSnp with Excl set to HIGH O...

Page 356: ...LI is implemented as a NOP 6 6 2 Data prefetching and monitoring The data cache implements an automatic prefetcher that monitors cache misses in the core When a pattern is detected the automatic prefetcher starts linefills in the background The prefetcher recognizes a sequence of data cache misses at a fixed stride pattern that lies in four cache lines plus or minus Any intervening stores or loads...

Page 357: ...ion Access Operation Rd Data Data Register 0 Read only MRS Xd S3_3_c15_c0_0 Data Data Register 1 Read only MRS Xd S3_3_c15_c0_1 Data Data Register 2 Read only MRS Xd S3_3_c15_c0_2 Data Data Register 3 Read only MRS Xd S3_3_c15_c0_3 Data Data Cache Tag Read Operation Register Write only MSR S3_3_c15_c2_0 Xd Set Way Instruction Cache Tag Read Operation Register Write only MSR S3_3_c15_c2_1 Xd Set Wa...

Page 358: ... Data cache size 4 Data cache reads return 64 bits of data in Data Register 0 and Data Register 1 The tag information MOESI coherency state outer attributes and valid for the selected cache line is returned using Data Register 0 and Data Register 1 using the format shown in Table 6 7 The Cortex A53 processor encodes the 4 bit MOESI coherency state across two fields of Data Register 0 and Data Regi...

Page 359: ... in the encodings and data format used in the CP15 operations used to access the tag and data memories Table 6 9 shows the encoding required to select a given cache line The set index range parameter S is determined by S log2 Instruction cache size Byte 2 32 for the 2 way set associative cache Data Register 0 3 Outer Allocation Hint Data Register 0 2 Outer Shareability from Dirty RAM Data Register...

Page 360: ...ate they can represent any combination of 16 bit and partial or full 32 bit instructions 6 7 3 TLB RAM accesses The Cortex A53 processor unified TLB is built from a 4 way set associative RAM based structure To read the individual entries into the data registers software must write to the TLB Data Read Operation Register Table 6 11 shows the write TLB Data Read Operation Register location encoding ...

Page 361: ... RAM 128 143 Walk cache RAM see Walk cache RAM on page 6 20 144 159 IPA cache RAM see IPA cache RAM on page 6 21 160 255 Unused Table 6 13 Main TLB descriptor data fields Bits Name Description 116 114 Parity ECC inclusion is processor configuration dependent If ECC is not configured these bits are absent 113 112 S2 Level The stage 2 level that gave this translation 0b00 No stage 2 translation perf...

Page 362: ...10 64KB 0b100 1MB 0b110 16MB VMSAv8 32 Long descriptor translation table format or VMSAv8 64 translation table format 0b001 4KB 0b011 64KB 0b101 2MB 0b111 512MB 55 40 ASID Address Space Identifier 39 32 VMID Virtual Machine Identifier 31 NS walk Security state that the entry was fetched in 30 2 VA Virtual Address 1 Address Sign bit VA 48 sign bit 0 Valid Valid bit 0 Entry does not contain valid da...

Page 363: ... Overridden Non coherent Outer WB Inner type 10 NC 11 WT Non coherent Outer NC 11 Non coherent Outer WT Inner type 00 NC 01 WB 10 WT Coherent Inner WB and Outer WB Inner allocation hint 00 NA 01 WA 10 RA 11 WRA 3 2 Device Device type 00 nGnRnE 01 nGnRE 10 nGRE 11 GRE Non coherent Outer WB Outer allocation hint 00 NA 01 WA 10 RA 11 WRA Non coherent Outer WT Coherent Inner WB and Outer WB Non cohere...

Page 364: ...ion level 83 60 VA Virtual address 59 56 Reserved must be zero 55 40 ASID Address Space Identifier 39 22 VMID Virtual Machine Identifier 31 NS walk Security state that the entry was fetched in 30 22 Reserved must be zero 21 18 Domain Valid only if the entry was fetched in VMSAv7 format 17 16 Entry size Memory size to which entry maps 0b00 1MB 0b01 2MB 0b10 512MB 0b11 Unused 15 NSTable Combined NST...

Page 365: ...ds Bits Name Description 116 114 ECC ECC If ECC is not configured these bits are absent 113 86 PA Physical address 85 62 IPA Unused lower bits page size dependent must be zero 61 59 Reserved must be zero 58 56 Size The size values are 0b011 64KB 0b101 2MB 0b111 512MB 55 40 Reserved must be zero 39 32 VMID Virtual Machine Identifier 31 11 Reserved must be zero 10 Contiguous Set if the pagewalk had ...

Page 366: ...em This chapter describes the L2 memory system It contains the following sections About the L2 memory system on page 7 2 Snoop Control Unit on page 7 3 ACE master interface on page 7 6 CHI master interface on page 7 13 Additional memory attributes on page 7 17 Optional integrated L2 cache on page 7 18 ACP on page 7 19 ...

Page 367: ...stem interfaces to the external memory system with either an AMBA 4 ACE bus or an AMBA 5 CHI bus All bus interfaces are 128 bits wide Optional tightly coupled L2 cache that includes Configurable L2 cache size of 128KB 256KB 512KB 1MB and 2MB Fixed line length of 64 bytes Physically indexed and tagged cache 16 way set associative cache structure Optional ACP interface if an L2 cache is configured O...

Page 368: ...SCU contains a set of duplicate tags that permit each coherent data request to be checked against the contents of the other caches in the cluster The duplicate tags filter coherent requests from the system so that the cores and system can function efficiently even with a high volume of snoops from the system When an external snoop hits in the duplicate tags a request is made to the appropriate cor...

Page 369: ...ntenance requests on AR channel No No Yes Yes Yes Snoops on AC channel No No No Yes Yes Coherent requests on AR or AW channel No No No Yes Yes DVM requests on AR channel No No No No Yes a Only true if SYSBARDISABLE is LOW If SYSBARDISABLE is HIGH then barriers are not broadcast Table 7 3 Supported CHI configurations Signal Feature CHI non coherent CHI outer coherent CHI inner coherent No L3 cache ...

Page 370: ...ches and maintenance operations are broadcast externally When you set the BROADCASTCACHEMAINT pin to 0 there are no downstream caches external to the Cortex A53 processor Note If you set the BROADCASTINNER pin to 1 you must also set the BROADCASTOUTER pin to 1 In a system that contains Cortex A53 processors and other processors in a big LITTLE configuration you must ensure the BROADCASTINNER and B...

Page 371: ...y mix of memory types is possible and each write can be a single write or a write burst Each core can also issue a barrier and the cluster can issue an additional barrier Read issuing capability 8n 4m 1 8 for each core in the cluster including up to 8 data linefills 4 non cacheable or Device data reads 1 non cacheable TLB page walk read 3 instruction linefills 5 coherency operations 1 barrier oper...

Page 372: ...D for both parts and therefore can have two outstanding transactions on the same ID Read ID width 6 The ID encodes the source of the memory transaction See Table 7 7 on page 7 8 a n is the number of cores m is 1 if the processor is configured with an ACP interface and 0 otherwise Table 7 5 ACE master interface attributes continued Attribute Valuea Comments Table 7 6 Encodings for AWIDM 4 0 Attribu...

Page 373: ...x A53 processor generates only a subset of all possible AXI transactions on the master interface For WriteBack transfers the supported transfers are WRAP 4 128 bit for read transfers linefills INCR 4 128 bit for write transfers evictions INCR N N 1 2 or 4 128 bit write transfers read allocate For Non cacheable transactions INCR N N 1 2 or 4 128 bit for write transfers INCR N N 1 2 or 4 128 bit for...

Page 374: ...ause there are many possibilities Table 7 8 ACE transactions Transaction Operation ReadNoSnoop Non cacheable loads or instruction fetches Linefills of non shareable cache lines into L1 or L2 ReadOnce Cacheable loads that are not allocating into the cache or cacheable instruction fetches when there is no L2 cache ReadClean Not used ReadNotSharedDirty Not used ReadShared L1 Data linefills started by...

Page 375: ...che the best case for response and data is 13 processor cycles When there is a miss in L2 cache and a hit in L1 cache the best case for response and data is 16 processor cycles Note Latencies can be higher if hazards occur or if there are not enough buffers to absorb requests Miss Best case six processor cycles when the SCU duplicate tags and L2 tags indicate the miss DVM The cluster takes a minim...

Page 376: ...e responses without delay by holding BREADY HIGH The ACE master asserts the write acknowledge signal WACK HIGH in the ACLK cycle following acceptance of a write response WACK is asserted in AXI3 compatibility mode in addition to ACE configurations Note For interoperability of system components ARM recommends that components interfacing with the ACE master are fully ACE compliant with no reliance o...

Page 377: ...or exception levels and corresponding ARPROTM 0 and AWPROTM 0 values Table 7 10 Cortex A53 MPCore mode and ARPROT and AWPROT values Processor exception level Type of access Value of ARPROT 0 and AWPROT 0 EL0 EL1 EL2 EL3 Cacheable read access Privileged access EL0 Device or normal Non cacheable read access Unprivileged access EL1 EL2 EL3 Privileged access EL0 EL1 EL2 EL3 Cacheable write access Priv...

Page 378: ...gured with four cores with L2 cache can issue 10 outstanding transactions A Cortex A53 processor configured with one core without L2 cache can issue five outstanding transactions All outstanding transactions use a unique ID Read issuing capability 8n 4m 1 8 for each core in the cluster including up to 8 data linefills 4 Non cacheable or Device data reads 1 Non cacheable TLB page walk read 3 instru...

Page 379: ...store instruction CleanUnique Store instructions that hit in the cache but the line is not in a unique coherence state MakeUnique Store instructions of a full cache line of data that miss in the caches and are allocating into the L2 cache CleanShared Cache maintenance instructions CleanInvalid Cache maintenance instructions MakeInvalid Cache maintenance instructions DVMOp TLB and instruction cache...

Page 380: ... is a miss in L2 cache and a hit in L1 cache the best case for response and data is 14 processor cycles Note Latencies can be higher if hazards occur or if there are not enough buffers to absorb requests Miss Best case six processor cycles when the SCU duplicate tags and L2 tags indicate the miss DVM The cluster takes a minimum of six cycles to provide a response to DVM packets Snoop filter Suppor...

Page 381: ...e marked as cacheable memory in the page tables and can take part in the cache coherency protocol Addresses that map to an HN I or MN must be marked as device or non cacheable memory Table 7 14 CHI transactions Transaction ID Description 000nnxxx Transaction from core nn Can be a Read transaction Write transaction Cache maintenance transaction DVM transaction Barrier transaction 001001xx Transacti...

Page 382: ...ts or bus protocols might require more information about the memory type and for these cases the cluster exports the unaltered memory attribute information from the translation tables stored in the TLB These signals are for information only and do not form part of the ACE or CHI protocols In an ACE configuration there is a RDMEMATTR bus for the read channel and a WRMEMATTR bus for the write channe...

Page 383: ...ng on the attributes of the memory region of the access All load accesses use the synchronous abort mechanism All STREX STREXB STREXH STREXD STXR STXRB STXRH STXP STLXR STLXRB STLXRH and STLXP instructions use the synchronous abort mechanism All store accesses to Device memory or Normal memory that is Inner Non cacheable Inner Write Through Outer Non cacheable or Outer Write Through use the asynch...

Page 384: ...t ARLEN and AWLEN are limited to values 0 and 3 This section describes ACP in Transfer size support ACP user signals on page 7 20 ACP performance on page 7 20 7 7 1 Transfer size support ACP supports the following read request transfer size and length combinations 64 byte INCR request characterized by ARLEN is 0x03 4 beats ARADDR aligned to 64 byte boundary so ARADDR 5 0 is 0b000000 ARSIZE and ARB...

Page 385: ...alling the interface until the first has completed If the master requires explicit ordering between two transactions ARM recommends that it waits for the response to the first transaction before sending the second transaction Writes are generally higher performance when they contain a full cache line of data If SCU cache protection is configured writes of less than 64 bits incur an additional over...

Page 386: ...M All rights reserved 8 1 ID021414 Non Confidential Chapter 8 Cache Protection This chapter describes the Cortex A53 CPU cache protection It contains the following sections Cache protection behavior on page 8 2 Error reporting on page 8 4 ...

Page 387: ...efore might cause data corruption If there are three or more bit errors then depending on the RAM and the position of the errors within the RAM the errors might be detected or might not be detected The Cortex A53 CPU cache protection support has a minimal performance impact when no errors are present When an error is detected the access that caused the error is stalled while the correction takes p...

Page 388: ...e other bits are performance hints therefore do not cause a functional failure if they are incorrect SCU L1 duplicate tag ECC SECDED CPU_CACHE_PROTECTION 33 bits Tag rewritten with correct value access retried If the error is uncorrectable then the tag is invalidated L2 tag ECC SECDED SCU_CACHE_PROTECTION 33 bits Tag rewritten with correct value access retried If the error is uncorrectable then th...

Page 389: ...maintenance operation or a snoop Uncorrectable errors in the L2 tag RAMs or SCU L1 duplicate tag RAMs causes the nINTERRIRQ pin to be asserted Note When nINTERRIRQ is asserted it remains asserted until the error is cleared by a write of 0 to the L2 internal asynchronous error bit of the L2ECTLR register ARM recommends that the nINTERRIRQ pin is connected to the interrupt controller so that an inte...

Page 390: ...ial Chapter 9 Generic Interrupt Controller CPU Interface This chapter describes the Cortex A53 processor implementation of the ARM Generic Interrupt Controller GIC CPU interface It contains the following sections About the GIC CPU Interface on page 9 2 GIC programmers model on page 9 3 ...

Page 391: ... functionality that supports Signaling interrupt groups to the target core using either the IRQ or the FIQ exception request based on software configuration A unified scheme for handling the priority of Group 0 and Group 1 interrupts This chapter describes only features that are specific to the Cortex A53 processor implementation 9 1 1 Bypassing the CPU Interface The GIC CPU Interface is always im...

Page 392: ...ry Each CPU interface block provides the interface for a Cortex A53 processor that interfaces with a GIC distributor within the system Each CPU interface provides a programming interface for Enabling the signaling of interrupt requests by the CPU interface Acknowledging an interrupt Indicating completion of the processing of an interrupt Setting an interrupt priority mask for the processor Definin...

Page 393: ... all configurations Attributes See the register summary in Table 9 2 The Cortex A53 processor implements the GICC_APR0 according to the recommendations described in the ARM Generic Interrupt Controller Architecture Specification Table 9 2 CPU interface register summary Name Type Reset Description GICC_CTLR RW 0x00000000 CPU Interface Control Register GICC_PMR RW 0x00000000 Interrupt Priority Mask ...

Page 394: ...ssible only by a hypervisor or similar software Table 9 3 Active Priority Register implementation Number of group priority bits Preemption levels Minimum legal value of Secure GICC_BPR Minimum legal value of Non secure GICC_BPR Active Priority Registers implemented View of Active Priority Registers for Non secure accesses 5 32 2 3 GICC_APR0 31 0 GICC_NSAPR0 31 16 appears as GICC_APR0 15 0 31 0 Rev...

Page 395: ...n number of priority bits number of preemption bits and number of List Registers implemented Usage constraints There are no usage constraints Configurations Available in all configurations Attributes See the register summary in Table 9 5 Figure 9 2 shows the GICH_VTR bit assignments Figure 9 2 GICH_VTR bit assignments Table 9 5 Virtual interface control register summary Name Type Reset Description...

Page 396: ...gnments Bit Name Description 31 29 PRIbits Indicates the number of priority bits implemented minus one 0x4 Five bits of priority and 32 priority levels 28 26 PREbits Indicates the number of preemption bits implemented minus one 0x4 Five bits of preemption and 32 preemption levels 25 6 Reserved RES0 5 0 ListRegs Indicates the number of implemented List Registers minus one 0x3 Four List Registers Ta...

Page 397: ...sage constraints Reading the content of this register and then writing the same values must not change any state because there is no requirement to preserve and restore state during a powerdown Configurations Available in all configurations Attributes See the register summary in Table 9 7 on page 9 7 The Cortex A53 processor implements the GICV_APR0 as an alias of GICH_APR0 VM CPU Interface Identi...

Page 398: ...ntial Chapter 10 Generic Timer This chapter describes the Cortex A53 processor implementation of the ARM Generic Timer It contains the following sections About the Generic Timer on page 10 2 Generic Timer functional description on page 10 3 Generic Timer register summary on page 10 4 ...

Page 399: ...d trigger interrupts based on an incrementing counter value It provides Generation of timer events as interrupt outputs Generation of event streams The Cortex A53 MPCore Generic Timer is compliant with the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile This chapter describes only features that are specific to the Cortex A53 MPCore implementation ...

Page 400: ...sed as a clock enable for the CNTVALUEB 63 0 registers This allows a multicycle path to be applied to the CNTVALUEB 63 0 bus Figure 10 1 shows the interface Figure 10 1 Architectural counter interface The value on the CNTVALUEB 63 0 bus is required to be stable whenever the internally registered version of the CNTCLKEN clock enable is asserted CNTCLKEN must be synchronous and balanced with CLK and...

Page 401: ...er Physical Timer TimerValue register CNTP_CTL_EL0 1 b 32 bit Counter timer Physical Timer Control register CNTP_CVAL_EL0 2 UNK 64 bit Counter timer Physical Timer CompareValue register CNTV_TVAL_EL0 c3 0 UNK 32 bit Counter timer Virtual Timer TimerValue register CNTV_CTL_EL0 1 b 32 bit Counter timer Virtual Timer Control register CNTV_CVAL_EL0 2 UNK 64 bit Counter timer Virtual Timer CompareValue...

Page 402: ...erValue register CNTP_CTL 1 b 32 bit Counter timer Physical Timer Control register CNTV_TVAL c3 0 UNK 32 bit Counter timer Virtual Timer TimerValue register CNTV_CTL 1 b 32 bit Counter timer Virtual Timer Control register CNTVCT 1 c14 UNK 64 bit Counter timer Virtual Count register CNTP_CVAL 2 UNK 64 bit Counter timer Physical Timer CompareValue register CNTV_CVAL 3 UNK 64 bit Counter timer Virtua...

Page 403: ...ons About debug on page 11 2 Debug register interfaces on page 11 4 AArch64 debug register summary on page 11 6 AArch64 debug register descriptions on page 11 8 AArch32 debug register summary on page 11 15 AArch32 debug register descriptions on page 11 17 Memory mapped register summary on page 11 21 Memory mapped register descriptions on page 11 25 Debug events on page 11 36 External debug interfa...

Page 404: ...bug This is invasive debug with the core running using a debug monitor that resides in memory Figure 11 1 shows a typical external debug system Figure 11 1 Typical debug system This typical system has several parts Debug host Protocol converter on page 11 3 Debug target on page 11 3 The debug unit on page 11 3 Self hosted debug on page 11 3 11 1 1 Debug host The debug host is a computer for exampl...

Page 405: ...otocol converter to access the debug unit using the Advanced Peripheral Bus APB slave interface 11 1 4 The debug unit The processor debug unit assists in debugging software running on the processor You can use the processor debug unit in combination with a software debugger program to debug Application software Operating systems Hardware systems based on an ARM processor The debug unit enables you...

Page 406: ...gisters This function is system register based and memory mapped You can access the debug register map using the APB slave port See External debug interface on page 11 37 Performance monitor This function is system register based and memory mapped You can access the performance monitor registers using the APB slave port See External debug interface on page 11 37 Trace registers This function is me...

Page 407: ... the first column a condition is true the entry gives the access permission of the register and scanning stops Table 11 1 External register conditions Name Condition Description Off EDPRSR PU is 0 Processor power domain is completely off or in a low power state where the processor power domain registers cannot be accessed Note If debug power is off then all external debug and memory mapped registe...

Page 408: ...isters EL1 on page 11 11 DBGBVR1_EL1 RW 64 Debug Breakpoint Value Register 1 DBGBCR1_EL1 RW 32 Debug Breakpoint Control Registers EL1 on page 11 8 DBGWVR1_EL1 RW 64 Debug Watchpoint Value Register 1 DBGWCR1_EL1 RW 32 Debug Watchpoint Control Registers EL1 on page 11 11 MDCCINT_EL1 RW 0x00000000 32 Monitor Debug Comms Channel Interrupt Enable Register MDSCR_EL1 RW 32 Monitor Debug System Register D...

Page 409: ...h Register MDRAR_EL1 RO a 64 Debug ROM Address Register OSLAR_EL1 WO 32 Debug OS Lock Access Register OSLSR_EL1 RO 0x0000000A 32 Debug OS Lock Status Register OSDLR_EL1 RW 0x00000000 32 Debug OS Double Lock Register DBGPRCR_EL1 RW 32 Debug Power Reset Control Register DBGCLAIMSET_EL1 RW 0x000000FF 32 Debug Claim Tag Set Register DBGCLAIMCLR_EL1 RW 0x00000000 32 Debug Claim Tag Clear Register DBGAU...

Page 410: ...CR_EL1 to form a Breakpoint Register Pair BRP DBGBVRn_EL1 is associated with DBGBCRn_EL1 to form BRPn Note The range of n for DBGBCRn_EL1 is 0 to 5 Usage constraints These registers are accessible as follows Configurations DBGBCRn_EL1 are architecturally mapped to The AArch32 DBGBCRn registers The external DBGBCRn_EL1 registers Attributes See the register summary in Table 11 3 on page 11 6 The deb...

Page 411: ...h context ID DBGBVRn_EL1 31 0 is a context ID 0b010 Address mismatch Mismatch address Behaves as type 0b000 if either In an AArch64 translation regime Halting debug mode is enabled and halting is allowed Otherwise DBGBVRn_EL1 is the address of an instruction to be stepped 0b100 Match VMID DBGBVRn_EL1 39 32 is a VMID 0b101 Match VMID and context ID DBGBVRn_EL1 31 0 is a context ID and DBGBVRn_EL1 3...

Page 412: ...r values are reserved Note The ARMv8 A architecture does not support direct execution of Java bytecodes BAS 3 and BAS 1 ignore writes and on reads return the values of BAS 2 and BAS 0 respectively 4 3 Reserved RES0 2 1 PMC Privileged Mode Control Determines the exception level or levels that a breakpoint debug event for breakpoint n is generated This field must be interpreted with the SSC and HMC ...

Page 413: ... DBGWCR_EL1 is UNKNOWN Figure 11 3 shows the DBGWCRn_EL1 bit assignments Figure 11 3 DBGWCRn_EL1 bit assignments Table 11 5 shows the DBGWCRn_EL1 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW BAS 31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0 RES0 WT SSC LSC MASK LBN HMC PAC RES0 E Table 11 5 DBGWCRn_EL1 bit assignments Bits Name Function 31 29 Reserved RES0 28 ...

Page 414: ...file for more information 15 14 SSC Security State Control This field enables the watchpoint to be conditional on the security state of the processor This field is used with the Hyp Mode Control HMC and Privileged Access Control PAC fields See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for possible values of the fields and the access modes and security states that...

Page 415: ... on any store Store Exclusive or swap 0b11 Match on all type of access 2 1 PAC Privileged Access Control This field enables watchpoint matching conditional on the mode of the processor This field is used with the SSC and PAC fields See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for possible values of the fields and the access modes and security states that can be ...

Page 416: ...o access the DBGCLAIMSET_EL1 in AArch64 Execution state read or write the register with MRS Xt DBGCLAIMSET_EL1 Read DBGCLAIMSET_EL1 into Xt MSR DBGCLAIMSET_EL1 Xt Write Xt to DBGCLAIMSET_EL1 The DBGCLAIMSET_EL1 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFA0 31 8 7 0 CLAIM RES0 Table 11 6 DBGCLAIMSET_EL1 bit assignments Bits Name Function ...

Page 417: ...ter Transmit Internal View DBGDTRRXint RO Debug Data Transfer Register Receive Internal View c0 0 c6 0 DBGWFARa RW Watchpoint Fault Address Register RES0 c0 0 c7 0 DBGVCR RW Debug Vector Catch Register c0 2 c0 0 DBGDTRRXext RW Debug Data Transfer Register Receive External View c0 2 c2 0 DBGDSCRext RW Debug Status and Control Register External View c0 2 c3 0 DBGDTRTXext RW Debug Data Transfer Regis...

Page 418: ...nded Value Register 5 0x300 c1 4 c0 0 DBGOSLAR WO Debug OS Lock Access Register c1 4 c1 0 DBGOSLSR RO Debug OS Lock Status Register c1 4 c3 0 DBGOSDLR RW Debug OS Double Lock Register 0x310 c1 4 c4 0 DBGPRCR RW Debug Power Reset Control Register c2 2 c0 0 DBGDSAR 31 0 b RO Debug Self Address Register RES0 0 c2 DBGDSAR 63 0 b RO c7 7 c0 0 DBGDEVID2 RO Debug Device ID Register 2 RES0 c7 7 c1 0 DBGDE...

Page 419: ...BGDIDR bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RO RO RO RO RO RO RO 31 28 27 24 23 20 19 16 15 14 13 12 11 0 WRPs BRPs CTX_CMPs Version RES0 DEVID_imp PCSR_imp SE nSUHD_imp Table 11 8 DBGDIDR bit assignments Bits Name Function 31 28 WRPs The number of Watchpoint Register Pairs WRPs implemented The number of implemented WRPs is one more than the value of this field T...

Page 420: ...es See the register summary in Table 11 7 on page 11 15 Figure 11 6 shows the DBGDEVID bit assignments Figure 11 6 DBGDEVID bit assignments 19 16 Version The Debug architecture version 0x6 The processor implements ARMv8 Debug architecture 15 DEVID_imp Reserved RAO 14 nSUHD_imp Secure User Halting Debug not implemented bit The value is 1 The processor does not implement Secure User Halting Debug 13...

Page 421: ...nted 27 24 AuxRegs Specifies support for the Debug External Auxiliary Control Register This value is 0x0 None supported 23 20 DoubleLock Specifies support for the Debug OS Double Lock Register This value is 0x1 The processor supports Debug OS Double Lock Register 19 16 VirExtns Specifies whether EL2 is implemented This value is 0x1 The processor implements EL2 15 12 VectorCatch Defines the form of...

Page 422: ...1 in AArch32 Execution state read the CP14 register with MRC p14 0 Rt c7 c1 47 Read Debug Device ID Register 1 RES0 31 0 PCSROffset 4 3 Table 11 10 DBGDEVID1 bit assignments Bits Name Function 31 4 Reserved RES0 3 0 Indicates the offset applied to PC samples returned by reads of EDPCSR The value is 0x2 EDPCSR samples have no offset applied and do not sample the instruction set state in the AArch32...

Page 423: ...nal Debug Instruction Transfer Register 0x088 EDSCR RW 32 External Debug Status and Control Register 0x08C DBGDTRTX_EL0 RW 32 Debug Data Transfer Register Transmit 0x090 EDRCR WO 32 External Debug Reserve Control Register 0x094 EDACR RW 32 External Debug Auxiliary Control Register 0x098 EDECCR RW 32 External Debug Exception Catch Control Register 0x09C 32 Reserved 0x0A0 EDPCSRlo RO 32 External Deb...

Page 424: ...VR4_EL1 63 32 0x448 DBGBCR4_EL1 RW 32 Debug Breakpoint Control Registers EL1 on page 11 8 0x44C Reserved 0x450 DBGBVR5_EL1 31 0 RW 64 Debug Breakpoint Value Register 5 0x454 DBGBVR5_EL1 63 32 0x458 DBGBCR5_EL1 RW 32 Debug Breakpoint Control Registers EL1 on page 11 8 0x45C 0x7FC Reserved 0x800 DBGWVR0_EL1 31 0 RW 64 Debug Watchpoint Value Register 0 0x804 DBGWVR0_EL1 63 32 0x808 DBGWCR0_EL1 RW 32 ...

Page 425: ... 0 RO 64 Processor Feature Register 1 RES0 0xD44 ID_AA64PFR1_EL1 63 32 0xD48 ID_AA64DFR1_EL1 31 0 RO 64 Debug Feature Register 1 RES0 0xD4C ID_AA64DFR1_EL1 63 32 0xD50 ID_AA64ISAR1_EL1 31 0 RO 64 Instruction Set Attribute Register 1 low word RES0 0xD54 ID_AA64ISAR1_EL1 63 32 0xD58 ID_AA64MMFR1_EL1 31 0 RO 64 Memory Model Feature Register 1 low word RES0 0xD5C ID_AA64MMFR1_EL1 63 32 0xD60 0xEFC Res...

Page 426: ... RO 32 Peripheral Identification Register 5 7 on page 11 31 0xFE0 EDPIDR0 RO 32 Peripheral Identification Register 0 on page 11 28 0xFE4 EDPIDR1 RO 32 Peripheral Identification Register 1 on page 11 28 0xFE8 EDPIDR2 RO 32 Peripheral Identification Register 2 on page 11 29 0xFEC EDPIDR3 RO 32 Peripheral Identification Register 3 on page 11 30 0xFF0 EDCIDR0 RO 32 Component Identification Register 0 ...

Page 427: ...ows Table 11 1 on page 11 5 describes the condition codes Configurations EDITCTRL is in the processor power domain Attributes See the register summary in Table 11 11 on page 11 21 Figure 11 8 shows the EDITCTRL bit assignments Figure 11 8 EDITCTRL bit assignments Table 11 12 shows the EDITCTRL bit assignments The EDITCTRL can be accessed through the internal memory mapped interface and the externa...

Page 428: ...tics are Purpose Provides extra information for external debuggers about features of the debug implementation Usage constraints This register is accessible as follows Table 11 1 on page 11 5 describes the condition codes Configurations The EDDEVID1 is in the Debug power domain Attributes See the register summary in Table 11 11 on page 11 21 Figure 11 10 on page 11 27 shows the EDDEVID1 bit assignm...

Page 429: ...al ID The Debug Peripheral ID registers are Peripheral Identification Register 0 on page 11 28 Peripheral Identification Register 1 on page 11 28 Peripheral Identification Register 2 on page 11 29 Peripheral Identification Register 3 on page 11 30 Peripheral Identification Register 4 on page 11 31 Peripheral Identification Register 5 7 on page 11 31 31 0 RES0 3 4 PCSROffset Table 11 14 EDDEVID1 bi...

Page 430: ...assignments The EDPIDR0 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFE0 Peripheral Identification Register 1 The EDPIDR1 characteristics are Purpose Provides information to identify an external debug component Usage constraints This register is accessible as follows Table 11 1 on page 11 5 describes the condition codes Configurations The E...

Page 431: ...sage constraints This register is accessible as follows Table 11 1 on page 11 5 describes the condition codes Configurations The EDPIDR2 is in the Debug power domain Attributes See the register summary in Table 11 11 on page 11 21 Figure 11 13 shows the EDPIDR2 bit assignments Figure 11 13 EDPIDR2 bit assignments RES0 31 0 3 4 Part_1 7 8 DES_0 Table 11 17 EDPIDR1 bit assignments Bits Name Function...

Page 432: ... domain Attributes See the register summary in Table 11 11 on page 11 21 Figure 11 14 shows the EDPIDR3 bit assignments Figure 11 14 EDPIDR3 bit assignments Table 11 19 shows the EDPIDR3 bit assignments The EDPIDR3 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFEC Table 11 18 EDPIDR2 bit assignments Bits Name Function 31 8 Reserved RES0 7 4 ...

Page 433: ...5 EDPIDR4 bit assignments Table 11 20 shows the EDPIDR4 bit assignments The EDPIDR4 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFD0 Peripheral Identification Register 5 7 No information is held in the Peripheral ID5 Peripheral ID6 and Peripheral ID7 Registers They are reserved for future use and are RES0 Off DLK OSLK EDAD SLK Default RO RE...

Page 434: ...ent Identification Register 3 on page 11 34 Component Identification Register 0 The EDCIDR0 characteristics are Purpose Provides information to identify an external debug component Usage constraints This register is accessible as follows Table 11 1 on page 11 5 describes the condition codes Configurations The EDCIDR0 is in the Debug power domain Attributes See the register summary in Table 11 11 o...

Page 435: ...r domain Attributes See the register summary in Table 11 11 on page 11 21 Figure 11 17 shows the EDCIDR1 bit assignments Figure 11 17 EDCIDR1 bit assignments Table 11 23 shows the EDCIDR1 bit assignments The EDCIDR1 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFF4 Component Identification Register 2 The EDCIDR2 characteristics are Purpose P...

Page 436: ...ternal memory mapped interface and the external debug interface offset 0xFF8 Component Identification Register 3 The EDCIDR3 characteristics are Purpose Provides information to identify an external debug component Usage constraints This register is accessible as follows Table 11 1 on page 11 5 describes the condition codes Configurations The EDCIDR3 is in the Debug power domain Attributes See the ...

Page 437: ...IDR3 bit assignments Table 11 25 shows the EDCIDR3 bit assignments The EDCIDR3 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFFC RES0 31 0 PRMBL_3 7 8 Table 11 25 EDCIDR3 bit assignments Bits Name Function 31 8 Reserved RES0 7 0 PRMBL_3 0xB1 Preamble byte 3 ...

Page 438: ...are always synchronous Memory hint instructions and cache clean operations except DC ZVA DC IVAC and DCIMVAC do not generate watchpoint debug events Store exclusive instructions generate a watchpoint debug event even when the check for the control of exclusive monitor fails For watchpoint debug events except those resulting from cache maintenance operations the value reported in DFAR is guaranteed...

Page 439: ...memory map The basic memory map supports up to four cores in the cluster Table 11 26 shows the address mapping for the Cortex A53 processor debug APB components when configured for v8 Debug memory map Each component in the table requires 4KB and uses the bottom 4KB of each 64KB region The remaining 60KB of each region is reserved DBGEN SPIDEN NIDEN SPNIDEN Authentication interface COMMTX COMMRX DC...

Page 440: ... PMU 0x240000 0x240FFF CPU 2 Trace 0x241000 0x30FFFF Reserved 0x310000 0x310FFF CPU 3 Debug 0x320000 0x320FFF CPU 3 CTI 0x330000 0x330FFF CPU 3 PMU 0x340000 0x340FFF CPU 3 Trace 0x341000 0x3FFFFF Reserved a Indicates the mapped component if present otherwise reserved Table 11 27 Address mapping for APB components Address offset 21 0 Componenta 0x00000 0x00FFF Cortex A53 APB ROM table 0x01000 0x07F...

Page 441: ...et If reset is asserted while an L1 data cache eviction or L1 data cache fetch is performed the accuracy of those cache entries is not guaranteed You must not use the DBGL1RSTDISABLE signal to disable automatic hardware controlled invalidation of the L1 data cache in normal processor powerup sequences This is because synchronisation of the L1 data cache invalidation sequence with the duplicate L1 ...

Page 442: ... a system peripheral 2 If step 1 involves any memory operation issue a DSB instruction 3 Issue an ISB instruction or exception entry or exception return 4 Poll the DBGAUTHSTATUS_EL1 to check whether the processor has already detected the changed value of these signals This is required because the system might not issue the signal change to the processor until several cycles after the DSB instructi...

Page 443: ...isters on page 11 42 0x004 ROMENTRY1 RO Core 0 CTI see ROM entry registers on page 11 42 0x008 ROMENTRY2 RO Core 0 PMU see ROM entry registers on page 11 42 0x00C ROMENTRY3 RO Core 0 ETM see ROM entry registers on page 11 42 0x010 ROMENTRY4 RO Core 1 Debug see ROM entry registers on page 11 42 0x014 ROMENTRY5 RO Core 1 CTI see ROM entry registers on page 11 42 0x018 ROMENTRY6 RO Core 1 PMU see ROM...

Page 444: ...er summary in Table 11 28 on page 11 41 Figure 11 21 shows the bit assignments for a ROMENTRY register Figure 11 21 ROMENTRY bit assignments 0xFDC ROMPIDR7 RO Peripheral Identification Register 5 7 on page 11 49 0xFE0 ROMPIDR0 RO Peripheral Identification Register 0 on page 11 45 0xFE4 ROMPIDR1 RO Peripheral Identification Register 1 on page 11 46 0xFE8 ROMPIDR2 RO Peripheral Identification Regist...

Page 445: ...ug component Note Negative values of address offsets are permitted using the two s complement of the offset 11 2 Reserved RES0 1 Format Format of the ROM table entry The value for all ROMENTRY registers is 0 End marker 1 32 bit format 0 Component presenta Indicates whether the component is present 0 Component is not present 1 Component is present a The components for core 0 are always present The ...

Page 446: ...1003 ROMENTRY3 Core 0 ETM trace unit 0x0001C 0x0001C003 ROMENTRY4 Core 1 Debug 0x00012 0x00012003a ROMENTRY5 Core 1 CTI 0x00019 0x00019003a ROMENTRY6 Core 1 PMU 0x00013 0x00013003a ROMENTRY7 Core 1 ETM trace unit 0x0001D 0x0001D003a ROMENTRY8 Core 2 Debug 0x00014 0x00014003a ROMENTRY9 Core 2 CTI 0x0001A 0x0001A003a ROMENTRY10 Core 2 PMU 0x00015 0x00015003a ROMENTRY11 Core 2 ETM trace unit 0x0001E ...

Page 447: ...ter 2 on page 11 47 Peripheral Identification Register 3 on page 11 47 Peripheral Identification Register 4 on page 11 48 Peripheral Identification Register 5 7 on page 11 49 Peripheral Identification Register 0 The ROMPIDR0 characteristics are Purpose Provides information to identify an external debug component Usage constraints This register is accessible as follows Table 11 1 on page 11 5 descr...

Page 448: ... codes Configurations The ROMPIDR1 is in the Debug power domain Attributes See the register summary in Table 11 28 on page 11 41 Figure 11 23 shows the ROMPIDR1 bit assignments Figure 11 23 ROMPIDR1 bit assignments Table 11 34 shows the ROMPIDR1 bit assignments RES0 31 0 7 8 Part_0 Table 11 33 ROMPIDR0 bit assignments Bits Name Function 31 8 Reserved RES0 7 0 Part_0 Least significant byte of the R...

Page 449: ...Figure 11 24 shows the ROMPIDR2 bit assignments Figure 11 24 ROMPIDR2 bit assignments Table 11 35 shows the ROMPIDR2 bit assignments The ROMPIDR2 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFE8 Peripheral Identification Register 3 The ROMPIDR3 characteristics are Purpose Provides information to identify an external debug component Usage co...

Page 450: ...face offset 0xFEC Peripheral Identification Register 4 The ROMPIDR4 characteristics are Purpose Provides information to identify an external debug component Usage constraints This register is accessible as follows Table 11 1 on page 11 5 describes the condition codes Configurations The ROMPIDR4 is in the Debug power domain Attributes See the register summary in Table 11 28 on page 11 41 Figure 11 ...

Page 451: ...e Component Identification Register 0 Component Identification Register 1 on page 11 50 Component Identification Register 2 on page 11 51 Component Identification Register 3 on page 11 51 Component Identification Register 0 The ROMCIDR0 characteristics are Purpose Provides information to identify an external debug component Usage constraints This register is accessible as follows Table 11 1 on pag...

Page 452: ...ffset 0xFF0 Component Identification Register 1 The ROMCIDR1 characteristics are Purpose Provides information to identify an external debug component Usage constraints This register is accessible as follows Table 11 1 on page 11 5 describes the condition codes Configurations The ROMCIDR1 is in the Debug power domain Attributes See the register summary in Table 11 28 on page 11 41 Figure 11 28 show...

Page 453: ...in Attributes See the register summary in Table 11 28 on page 11 41 Figure 11 29 shows the ROMCIDR2 bit assignments Figure 11 29 ROMCIDR2 bit assignments Table 11 41 shows the ROMCIDR2 bit assignments The ROMCIDR2 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFF8 Component Identification Register 3 The ROMCIDR3 characteristics are Purpose Pr...

Page 454: ...tes See the register summary in Table 11 28 on page 11 41 Figure 11 30 shows the ROMCIDR3 bit assignments Figure 11 30 ROMCIDR3 bit assignments Table 11 42 shows the ROMCIDR3 bit assignments The ROMCIDR3 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFFC Off DLK OSLK EDAD SLK Default RO RES0 31 0 PRMBL_3 7 8 Table 11 42 ROMCIDR3 bit assignmen...

Page 455: ...ing sections About the PMU on page 12 2 PMU functional description on page 12 3 AArch64 PMU register summary on page 12 5 AArch64 PMU register descriptions on page 12 7 AArch32 PMU register summary on page 12 14 AArch32 PMU register descriptions on page 12 16 Memory mapped register summary on page 12 23 Memory mapped register descriptions on page 12 26 Events on page 12 36 Interrupts on page 12 40...

Page 456: ...s statistics on the operation of the processor and its memory system during runtime These provide useful information about the behavior of the processor that you can use when debugging or profiling code The PMU provides six counters Each counter can count any of the events available in the processor The absolute counts recorded might vary because of pipeline effects This has negligible effect exce...

Page 457: ...sters using the system registers or external APB interface 12 2 3 Counters The PMU has 32 bit counters that increment when they are enabled based on events and a 64 bit cycle counter 12 2 4 PMU register interfaces The Cortex A53 processor supports access to the performance monitor registers from the internal system register interface and a memory mapped interface External access to the performance...

Page 458: ...gister access permission and scanning stops Table 12 1 External register conditions Name Condition Description Off EDPRSR PU is 0 Processor power domain is completely off or in a low power state where the processor power domain registers cannot be accessed DLK EDPRSR DLK is 1 OS Double Lock is locked OSLK OSLSR_EL1 OSLK is 1 OS Lock is locked EPMAD AllowExternalPMUAccess FALSE External performance...

Page 459: ... Register PMSWINC_EL0 WO 32 Performance Monitors Software Increment Register PMSELR_EL0 RW 32 Performance Monitors Event Counter Selection Register PMCEID0_EL0 RO 32 Performance Monitors Common Event Identification Register 0 on page 12 9 PMCEID1_EL0 RO 32 Performance Monitors Common Event Identification Register 1 on page 12 12 PMCCNTR_EL0 RW 64 Performance Monitors Cycle Count Register PMXEVTYPE...

Page 460: ...EL0 RW 32 Performance Monitors Event Type Registers PMEVTYPER1_EL0 RW 32 PMXVTYPER2_EL0 RW 32 PMEVTYPER3_EL0 RW 32 PMEVTYPER4_EL0 RW 32 PMEVTYPER5_EL0 RW 32 PMCCFILTR_EL0 RW 32 Performance Monitors Cycle Count Filter Register Table 12 3 PMU register summary in the AArch64 Execution state continued Name Type Width Description ...

Page 461: ...ly mapped to the AArch32 PMCR register See Performance Monitors Control Register on page 12 16 Attributes PMCR_EL0 is a 32 bit register Figure 12 2 shows the PMCR_EL0 bit assignments Figure 12 2 PMCR_EL0 bit assignments Table 12 4 shows the PMCR_EL0 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 RW RW RW RW RW RW E 31 24 23 16 15 11 10 6 5 4 3 2 1 0 IMP IDCODE N RES0 DP X D C P LC ...

Page 462: ...lock cycle This is the reset value 1 When enabled PMCCNTR_EL0 counts every 64 clock cycles This bit is read write 2 C Clock counter reset This bit is WO The effects of writing to this bit are 0 No action This is the reset value 1 Reset PMCCNTR_EL0 to 0 This bit is always RAZ Note Resetting PMCCNTR does not clear the PMCCNTR_EL0 overflow bit to 0 See the ARM Architecture Reference Manual ARMv8 for ...

Page 463: ...pped to The AArch32 register PMCEID0 See Performance Monitors Common Event Identification Register 0 on page 12 18 The external register PMCEID0_EL0 Attributes PMCEID0_EL0 is a 32 bit register Figure 12 3 shows the PMCEID0_EL0 bit assignments Figure 12 3 PMCEID0_EL0 bit assignments Table 12 6 on page 12 10 shows the PMCEID0_EL0 bit assignments EL0 EL1 NS EL1 S EL2 EL3 SCR NS 1 EL3 SCR NS 0 Config ...

Page 464: ...nted 24 0x18 L2D_CACHE_WB L2 Data cache Write Back 0 This event is not implemented if the Cortex A53 processor has been configured without an L2 cache 1 This event is implemented if the Cortex A53 processor has been configured with an L2 cache 23 0x17 L2D_CACHE_REFILL L2 Data cache refill 0 This event is not implemented if the Cortex A53 processor has been configured without an L2 cache 1 This eve...

Page 465: ...pass write to CONTEXTIDR 1 This event is implemented 10 0x0A EXC_RETURN Instruction architecturally executed condition check pass exception return 1 This event is implemented 9 0x09 EXC_TAKEN Exception taken 1 This event is implemented 8 0x08 INST_RETIRED Instruction architecturally executed 1 This event is implemented 7 0x07 ST_RETIRED Instruction architecturally executed condition check pass sto...

Page 466: ...age constraints This register is accessible as follows This register is accessible at EL0 when PMUSERENR_EL0 EN is set to 1 Configurations The PMCEID1_EL0 is architecturally mapped to The AArch32 register PMCEID1 See Performance Monitors Common Event Identification Register 1 on page 12 21 The external register PMCEID1_EL0 Attributes PMCEID1_EL0 is a 32 bit register Figure 12 4 shows the PMCEID1_E...

Page 467: ...L0 MRS Xt PMCEID1_EL0 Read Performance Monitor Common Event Identification Register 0 The PMCEID1_EL0 can be accessed through the internal memory mapped interface and the external debug interface offset 0xE24 Table 12 8 PMU common events Bit Event number Event mnemonic Description 0 0x20 L2D_CACHE_ALLOCATE 0 This event is not implemented ...

Page 468: ...onitors Count Enable Clear Register c9 0 c12 3 PMOVSR RW 32 Performance Monitors Overflow Flag Status Register c9 0 c12 4 PMSWINC WO 32 Performance Monitors Software Increment Register c9 0 c12 5 PMSELR RW 32 Performance Monitors Event Counter Selection Register c9 0 c12 6 PMCEID0 RO 32 Performance Monitors Common Event Identification Register 0 on page 12 18 c9 0 c12 7 PMCEID1 RO 32 Performance M...

Page 469: ...ors Event Type Registers c14 0 c12 1 PMEVTYPER1 RW 32 c14 0 c12 2 PMEVTYPER2 RW 32 c14 0 c12 3 PMEVTYPER3 RW 32 c14 0 c12 4 PMEVTYPER4 RW 32 c14 0 c12 5 PMEVTYPER5 RW 32 c14 0 c15 7 PMCCFILTR RW 32 Performance Monitors Cycle Count Filter Register Table 12 9 PMU register summary in the AArch32 Execution state continued CRn Op1 CRm Op2 Name Type Width Description ...

Page 470: ...ERENR_EL0 EN is set to 1 Configurations The PMCR is architecturally mapped to The AArch64 PMCR_EL0 register See Performance Monitors Control Register on page 12 7 The external PMCR_EL0 register There is one copy of this register that is used in both Secure and Non secure states Attributes PMCR is a 32 bit register Figure 12 5 shows the PMCR bit assignments Figure 12 5 PMCR bit assignments Table 12...

Page 471: ...MCCNTR_EL0 counts every clock cycle This is the reset value 1 When enabled PMCCNTR_EL0 counts every 64 clock cycles This bit is read write 2 C Clock counter reset This bit is WO The effects of writing to this bit are 0 No action This is the reset value 1 Reset PMCCNTR_EL0 to 0 This bit is always RAZ Note Resetting PMCCNTR does not clear the PMCCNTR_EL0 overflow bit to 0 See the ARM Architecture Re...

Page 472: ...ID0_EL0 There is one copy of this register that is used in both Secure and Non secure states Attributes PMCEID0 is a 32 bit register Figure 12 6 shows the PMCEID0 bit assignments Figure 12 6 PMCEID0 bit assignments Table 12 11 shows the PMCEID0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0 See the ARM Architecture Reference Manual ARMv8 for ARMv...

Page 473: ...d 24 0x18 L2D_CACHE_WB L2 Data cache Write Back 0 This event is not implemented if the Cortex A53 processor has been configured without an L2 cache 1 This event is implemented if the Cortex A53 processor has been configured with an L2 cache 23 0x17 L2D_CACHE_REFILL L2 Data cache refill 0 This event is not implemented if the Cortex A53 processor has been configured without an L2 cache 1 This event ...

Page 474: ...his event is implemented 10 0x0A EXC_RETURN Instruction architecturally executed condition check pass exception return 1 This event is implemented 9 0x09 EXC_TAKEN Exception taken 1 This event is implemented 8 0x08 INST_RETIRED Instruction architecturally executed 1 This event is implemented 7 0x07 ST_RETIRED Instruction architecturally executed condition check pass store 1 This event is implement...

Page 475: ...e Performance Monitors Common Event Identification Register 1 on page 12 12 The external register PMCEID1_EL0 There is one copy of this register that is used in both Secure and Non secure states Attributes PMCEID1 is a 32 bit register Figure 12 7 shows the PMCEID1 bit assignments Figure 12 7 PMCEID1 bit assignments Table 12 13 shows the PMCEID1 bit assignments EL0 NS EL0 S EL1 NS EL1 S EL2 EL3 SCR...

Page 476: ... 2013 2014 ARM All rights reserved 12 22 ID021414 Non Confidential To access the PMCEID1 MRC p15 0 Rt c9 c12 7 Read PMCEID1 into Rt The PMCEID1 can be accessed through the internal memory mapped interface and the external debug interface offset 0xE24 ...

Page 477: ... Reserved 0x018 PMEVCNTR3_EL0 RW Performance Monitor Event Count Register 3 0x01C Reserved 0x020 PMEVCNTR4_EL0 RW Performance Monitor Event Count Register 4 0x024 Reserved 0x028 PMEVCNTR5_EL0 RW Performance Monitor Event Count Register 5 0x02C 0xF4 Reserved 0x0F8 PMCCNTR_EL0 31 0 RW Performance Monitor Cycle Count Register 0x0FC PMCCNTR_EL0 63 32 RW 0x100 0x3FC Reserved 0x400 PMEVTYPER0_EL0 RW Per...

Page 478: ...ce Monitors Device Affinity Register 0 see Multiprocessor Affinity Register on page 4 15 0xFAC PMDEVAFF1 RO Performance Monitors Device Affinity Register 1 RES0 0xFB0 PMLAR WO Performance Monitor Lock Access Register 0xFB4 PMLSR RO Performance Monitor Lock Status Register 0xFB8 PMAUTHSTATUS RO Performance Monitor Authentication Status Register 0xFBC PMDEVARCH Performance Monitor Device Architectur...

Page 479: ...ification Register 1 on page 12 32 0xFF8 PMCIDR2 RO Component Identification Register 2 on page 12 33 0xFFC PMCIDR3 RO Component Identification Register 3 on page 12 34 a This register is distinct from the PMCR_EL0 system register It does not have the same value Table 12 15 Memory mapped PMU register summary continued Offset Name Type Description ...

Page 480: ...es Configurations The PMCFGR is in the processor power domain Attributes See the register summary in Table 12 15 on page 12 23 Figure 12 8 shows the PMCFGR bit assignments Figure 12 8 PMCFGR bit assignments Table 12 16 shows the PMCFGR bit assignments Off DLK OSLK EPMAD SLK Default Error Error Error Error RO RO 31 17 16 15 14 13 8 7 0 N EX CCD CC RES0 Size Table 12 16 PMCFGR bit assignments Bits N...

Page 481: ...12 28 Peripheral Identification Register 2 on page 12 29 Peripheral Identification Register 3 on page 12 30 Peripheral Identification Register 4 on page 12 30 Peripheral Identification Register 5 7 on page 12 31 Peripheral Identification Register 0 The PMPIDR0 characteristics are Purpose Provides information to identify a Performance Monitor component Usage constraints The PMPIDR0 can be accessed ...

Page 482: ...on to identify a Performance Monitor component Usage constraints The PMPIDR1 can be accessed through the internal memory mapped interface and the external debug interface The accessibility to the PMPIDR1 by condition code is Table 12 1 on page 12 4 describes the condition codes Configurations The PMPIDR1 is in the Debug power domain Attributes See the register summary in Table 12 15 on page 12 23 ...

Page 483: ... the external debug interface Configurations The PMPIDR2 is in the Debug power domain Attributes See the register summary in Table 12 15 on page 12 23 Figure 12 11 shows the PMPIDR2 bit assignments Figure 12 11 PMPIDR2 bit assignments Table 12 20 shows the PMPIDR2 bit assignments Table 12 19 PMPIDR1 bit assignments Bits Name Function 31 8 Reserved RES0 7 4 DES_0 0xB ARM Limited This is the least s...

Page 484: ...he PMPIDR3 is in the Debug power domain Attributes See the register summary in Table 12 15 on page 12 23 Figure 12 12 shows the PMPIDR3 bit assignments Figure 12 12 PMPIDR3 bit assignments Table 12 21 shows the PMPIDR3 bit assignments The PMPIDR3 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFEC Peripheral Identification Register 4 The PMPID...

Page 485: ...ion is held in the Peripheral ID5 Peripheral ID6 and Peripheral ID7 Registers They are reserved for future use and are RES0 12 8 3 Component Identification Registers There are four read only Component Identification Registers Component ID0 through Component ID3 Table 12 23 shows these registers Off DLK OSLK EPMAD SLK Default RO RO RES0 31 0 3 4 DES_2 7 8 Size Table 12 22 PMPIDR4 bit assignments Bi...

Page 486: ...lity to the PMCIDR0 by condition code is Table 12 1 on page 12 4 describes the condition codes Configurations The PMCIDR0 is in the Debug power domain Attributes See the register summary in Table 12 15 on page 12 23 Figure 12 14 shows the PMCIDR0 bit assignments Figure 12 14 PMCIDR0 bit assignments Table 12 24 shows the PMCIDR0 bit assignments The PMCIDR0 can be accessed through the internal memor...

Page 487: ...omponent Identification Register 2 The PMCIDR2 characteristics are Purpose Provides information to identify a Performance Monitor component Usage constraints The PMCIDR2 can be accessed through the internal memory mapped interface and the external debug interface The accessibility to the PMCIDR2 by condition code is Table 12 1 on page 12 4 describes the condition codes Configurations The PMCIDR2 i...

Page 488: ...nternal memory mapped interface and the external debug interface The accessibility to the PMCIDR3 by condition code is Table 12 1 on page 12 4 describes the condition codes Configurations The PMCIDR3 is in the Debug power domain Attributes See the register summary in Table 12 15 on page 12 23 Figure 12 17 shows the PMCIDR3 bit assignments Figure 12 17 PMCIDR3 bit assignments Table 12 27 shows the ...

Page 489: ...tor Unit ARM DDI 0500D Copyright 2013 2014 ARM All rights reserved 12 35 ID021414 Non Confidential The PMCIDR3 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFFC ...

Page 490: ...ETIRED 5 5 Instruction architecturally executed condition check pass load 0x07 ST_RETIRED 6 6 Instruction architecturally executed condition check pass store 0x08 INST_RETIRED 7 7 Instruction architecturally executed 0x09 EXC_TAKEN 9 9 Exception taken 0x0A EXC_RETURN 10 10 Exception return 0x0B CID_WRITE_RETIRED 11 11 Change to Context ID retired 0x0C PC_WRITE_RETIRED 12 12 Instruction architectur...

Page 491: ... Non cacheable external memory request 0xC2 Linefill because of prefetch 0xC3 Instruction Cache Throttle occurred 0xC4 Entering read allocate mode 0xC5 Read allocate mode 0xC6 Pre decode error 0xC7 Data Write operation that stalls the pipeline because the store buffer is full 0xC8 SCU Snooped data from another CPU for this CPU 0xC9 Conditional branch executed 0xCA Indirect branch mispredicted 0xCB...

Page 492: ...k that is not because of an Advanced SIMD or Floating point instruction and not because of a load store instruction waiting for data to calculate the address in the AGU Stall cycles because of a stall in Wr typically awaiting load data are excluded 0xE5 Attributable Performance Impact Event Counts every cycle there is an interlock that is because of a load store instruction waiting for data to cal...

Page 493: ...ecuted Counts every cycle in which two instructions are architecturally retired Event 0x08 INTR_RETIRED always counts when this event counts 26 26 L2 data or tag memory error correctable or non correctable 27 27 SCU snoop filter memory error correctable or non correctable 28 Advanced SIMD and Floating point retention active 29 CPU retention active Table 12 28 PMU events continued Event number Even...

Page 494: ...ocessor asserts the nPMUIRQ signal when an interrupt is generated by the PMU You can route this signal to an external interrupt controller for prioritization and masking This is the only mechanism that signals this interrupt to the processor This interrupt is also driven as a trigger input to the CTI See Chapter 14 Cross Trigger for more information ...

Page 495: ...dition to the counters in the processor some of the events that Table 12 28 on page 12 36 describes are exported on the PMUEVENT bus and can be connected to external hardware 12 11 2 Debug trace hardware Some of the events that Table 12 28 on page 12 36 describes are exported to the ETM trace unit or to the Cross Trigger Interface CTI to enable the events to be monitored See Chapter 13 Embedded Tr...

Page 496: ...ns the following sections About the ETM on page 13 2 ETM trace unit generation options and resources on page 13 3 ETM trace unit functional description on page 13 5 Reset on page 13 7 Modes of operation and execution on page 13 8 ETM trace unit register interfaces on page 13 9 ETM register summary on page 13 10 ETM register descriptions on page 13 13 Interaction with debug and performance monitori...

Page 497: ...e ETM trace unit is a module that performs real time instruction flow tracing based on the Embedded Trace Macrocell ETM architecture ETMv4 ETM is a CoreSight component and is an integral part of the ARM Real time Debug solution DS 5 Development Studio See the CoreSight documentation in Additional reading on page ix for more information ...

Page 498: ...emented Support for tracing of load and store instructions as P0 elements Not implemented Support for cycle counting in the instruction trace Implemented Support for branch broadcast tracing Implemented Exception Levels implemented in Non secure state EL2 EL1 EL0 Exception Levels implemented in Secure state EL3 EL1 EL0 Number of events supported in the trace 4 Return stack support Implemented Trac...

Page 499: ...ors implemented 4 Number of external inputs implemented 30 4 CTI 26 PMU Number of counters implemented 2 Reduced function counter implemented Not implemented Number of sequencer states implemented 4 Number of Virtual Machine ID comparators implemented 1 Number of Context ID comparators implemented 1 Number of address comparator pairs implemented 4 Number of single shot comparator controls 1 Number...

Page 500: ... trace packets based on P0 elements 13 3 3 Filtering and triggering resources You can limit the amount of trace data generated by the ETM through the process of filtering For example generating trace only in a certain address range More complicated logic analyzer style filtering options are also available The ETM trace unit can also generate a trigger that is a signal to the trace capture device t...

Page 501: ...ht 2013 2014 ARM All rights reserved 13 6 ID021414 Non Confidential 13 3 5 Trace out Trace from FIFO is output on the synchronous AMBA ATB interface 13 3 6 Syncbridge The ATB interface from the trace out block goes through an ATB synchronous bridge ...

Page 502: ...the processor The ETM trace unit is not reset when warm reset is applied to the processor so that tracing through warm processor reset is possible If the ETM trace unit is reset tracing stops until the ETM trace unit is reprogrammed and re enabled However if the processor is reset using warm reset the last few instructions provided by the processor before the reset might not be traced ...

Page 503: ...nit main enable in the TRCPRGCTLR to disable all trace operations during programming See Programming Control Register on page 13 13 Figure 13 2 shows the procedure to follow Figure 13 2 Programming ETM trace unit registers The Cortex A53 processor does not have to be in the debug state while you program the ETM trace unit registers 13 5 2 Programming and reading ETM trace unit registers You progra...

Page 504: ...rfaces The Cortex A53 processor supports only memory mapped interface to trace registers For more information see External debug interface on page 11 37 13 6 1 Access permissions See the ARM ETM Architecture Specification ETMv4 for information on the behaviors on register accesses for different trace unit states and the different access mechanisms ...

Page 505: ...r on page 13 13 TRCSTATR RO Status Register on page 13 13 TRCCONFIGR RW Trace Configuration Register on page 13 14 TRCAUXCTLR RW Auxiliary Control Register on page 13 16 TRCEVENTCTL0R RW Event Control 0 Register on page 13 18 TRCEVENTCTL1R RW Event Control 1 Register on page 13 19 TRCSTALLCTLR RW Stall Control Register on page 13 20 TRCTSCTLR RW Global Timestamp Control Register on page 13 21 TRCS...

Page 506: ...e 13 38 TRCIDR0 RO ID Register 0 on page 13 38 TRCIDR1 RO ID Register 1 on page 13 40 TRCIDR2 RO ID Register 2 on page 13 40 TRCIDR3 RO ID Register 3 on page 13 41 TRCIDR4 RO ID Register 4 on page 13 43 TRCIDR5 RO ID Register 5 on page 13 44 TRCRSCTLRn RW Resource Selection Control Registers 2 16 on page 13 45 n is 2 15 TRCSSCCR0 RW Single Shot Comparator Control Register 0 on page 13 46 TRCSSCSR0...

Page 507: ...egister on page 13 64 TRCAUTHSTATUS RO Authentication Status Register on page 13 65 TRCDEVARCH RO Device Architecture Register on page 13 66 TRCDEVID RO Device ID Register on page 13 67 TRCDEVTYPE RO Device Type Register on page 13 67 TRCPIDR4 RO Peripheral Identification Register 4 on page 13 71 TRCPIDR5 RO Peripheral Identification Register 5 7 on page 13 72 TRCPIDR6 RO TRCPIDR7 RO TRCPIDR0 RO P...

Page 508: ...igure 13 3 TRCPRGCTLR bit assignments Table 13 4 shows the TRCPRGCTLR bit assignments The TRCPRGCTLR can be accessed through the internal memory mapped interface and the external debug interface offset 0x004 13 8 2 Status Register The TRCSTATR characteristics are Purpose Indicates the ETM trace unit status Usage constraints There are no usage constraints Configurations Available in all configurati...

Page 509: ...ation Only accepts writes when the trace unit is disabled Configurations Available in all configurations Attributes TRCCONFIGR is a 32 bit RW trace register See the register summary in Table 13 3 on page 13 10 Figure 13 5 shows the TRCCONFIGR bit assignments Figure 13 5 TRCCONFIGR bit assignments 31 1 0 IDLE RES0 2 PMSTABLE Table 13 5 TRCSTATR bit assignments Bits Name Function 31 2 Reserved RES0 ...

Page 510: ...16 shows the TRCBBCTLR bit assignments Table 13 6 TRCCONFIGR bit assignments Bits Name Function 31 13 Reserved RES0 12 RS Enables the return stack The possible values are 0 Disables the return stack 1 Enables the return stack 11 TS Enables global timestamp tracing The possible values are 0 Disables global timestamp tracing 1 Enables global timestamp tracing 10 8 Reserved RES0 7 VMID Enables VMID t...

Page 511: ... 7 RANGE 9 MODE Table 13 7 TRCBBCTLR bit assignments Bits Name Function 31 9 Reserved RES0 8 MODE Mode bit 0 Exclude mode Branch broadcasting is not enabled in the address range that RANGE defines If RANGE 0 then branch broadcasting is enabled for the entire memory map 1 Include mode Branch broadcasting is enabled in the address range that RANGE defines If RANGE 0 then the behavior of the trace un...

Page 512: ...trace on de assertion of authentication inputs The possible values are 0 ETM trace unit FIFO is flushed and ETM trace unit enters idle state when DBGEN or NIDEN is LOW 1 ETM trace unit FIFO is not flushed and ETM trace unit does not enter idle state when DBGEN or NIDEN is LOW When this bit is set to 1 the trace unit behavior deviates from architecturally specified behavior 4 TSNODELAY Do not delay...

Page 513: ...layed 1 Forces FIFO overflow when SYNC packets are delayed When this bit is set to 1 the trace unit behavior deviates from architecturally specified behavior 1 IDLEACK Force idle drain acknowledge high CPU does not wait for trace to drain before entering WFX state The possible values are 0 ETM trace unit idle acknowledge is asserted only when the ETM trace unit is in idle state 1 ETM trace unit id...

Page 514: ...PE3 is 1 selects a Boolean combined resource pair from 0 7 defined by bits 2 0 23 TYPE2 Selects the resource type for trace event 2 0 Single selected resource 1 Boolean combined resource pair 22 20 Reserved RES0 19 16 SEL2 Selects the resource number based on the value of TYPE2 When TYPE2 is 0 selects a single selected resource from 0 15 defined by bits 3 0 When TYPE2 is 1 selects a Boolean combin...

Page 515: ...s register as part of trace unit initialization Accepts writes only when the trace unit is disabled Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 10 on page 13 21 shows the TRCSTALLCTLR bit assignments 31 0 RES0 4 3 5 8 7 EN 12 11 10 RES0 ATB 13 LPOVERRIDE Table 13 10 TRCEVENTCL1R bit assignments Bits Name Function 31 13 Re...

Page 516: ...igurations Available in all configurations Attributes TRCTSCTLR is a 32 bit RW trace register The register is set to an UNKNOWN value on a trace unit reset See also Table 13 3 on page 13 10 Figure 13 11 shows the TRCTSCTLR bit assignments Figure 13 11 TRCTSCTLR bit assignments RES0 31 0 7 4 LEVEL 3 ISTALL 8 9 LEVEL RES0 Table 13 11 TRCSTALLCTLR bit assignments Bits Name Function 31 9 Reserved RES0...

Page 517: ...13 13 shows the TRCSYNCPR bit assignments The TRCSYNCPR can be accessed through the internal memory mapped interface and the external debug interface offset 0x034 Table 13 12 TRCTSCTLR bit assignments Bits Name Function 31 8 Reserved RES0 7 TYPE Single or combined resource selector 6 4 Reserved 3 1 SEL Identifies the resource selector to use 31 0 RES0 4 5 Period Table 13 13 TRCSYNCPR bit assignmen...

Page 518: ... the TRCCCCTLR bit assignments The TRCCCCTLR can be accessed through the internal memory mapped interface and the external debug interface offset 0x038 13 8 12 Trace ID Register The TRCTRACEIDR characteristics are Purpose Sets the trace ID for instruction trace Usage constraints You must always program this register as part of trace unit initialization Accepts writes only when the trace unit is di...

Page 519: ...is disabled Returns stable data only when TRCSTATR PMSTABLE 1 Must be programmed particularly to set the value of the SSSTATUS bit that sets the state of the start stop logic Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 15 shows the TRCVICTLR bit assignments Figure 13 15 TRCVICTLR bit assignments Table 13 15 TRCTRACEIDR bi...

Page 520: ...ace unit generates instruction trace in Secure state for exception level n 1 Trace unit does not generate instruction trace in Secure state for exception level n Note The exception levels are Bit 16 Exception level 0 Bit 17 Exception level 1 Bit 18 RAZ WI Instruction tracing is not implemented for exception level 2 Bit 19 Exception level 3 15 12 Reserved RES0 11 TRCERR Selects whether a system err...

Page 521: ...ects the resource type for the viewinst event 0 Single selected resource 1 Boolean combined resource pair 6 4 Reserved RES0 3 0 SEL Selects the resource number to use for the viewinst event based on the value of TYPE When TYPE is 0 selects a single selected resource from 0 15 defined by bits 3 0 When TYPE is 1 selects a Boolean combined resource pair from 0 7 defined by bits 2 0 Table 13 16 TRCVIC...

Page 522: ...erface and the external debug interface offset 0x088 13 8 16 Sequencer State Transition Control Registers 0 2 The TRCSEQEVRn characteristics are Purpose Defines the sequencer transitions that progress to the next state or backwards to the previous state The ETM trace unit implements a sequencer state machine with up to four states Usage constraints Accepts writes only when the trace unit is disabl...

Page 523: ...ons Attributes See the register summary in Table 13 3 on page 13 10 31 0 RES0 16 B SEL F SEL 15 8 7 11 12 14 4 3 6 B TYPE F TYPE RES0 RES0 Table 13 19 TRCSEQEVRn bit assignments Bits Name Function 31 16 Reserved RES0 15 B TYPE Selects the resource type to move backwards to this state from the next state 0 Single selected resource 1 Boolean combined resource pair 14 12 Reserved RES0 11 8 B SEL Sele...

Page 524: ... Software must use this register to set the initial state of the sequencer before the sequencer is used Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 20 shows the TRCSEQSTR bit assignments Figure 13 20 TRCSEQSTR bit assignments 31 0 RES0 RES0 RESETSEL 8 7 4 3 6 RESETTYPE Table 13 20 TRCSEQRSTEVR bit assignments Bits Name Fu...

Page 525: ... Table 13 3 on page 13 10 Figure 13 21 shows the TRCEXTINSELR bit assignments Figure 13 21 TRCEXTINSELR bit assignments Table 13 22 shows the TRCEXTINSELR bit assignments Table 13 21 TRCSEQSTR bit assignments Bits Name Function 31 2 Reserved RES0 1 0 STATE Current sequencer state b00 State 0 b01 State 1 b10 State 2 b11 State 3 31 0 8 7 16 15 24 23 SEL2 SEL1 SEL0 SEL3 28 29 RES0 RES0 20 21 RES0 12 ...

Page 526: ...LDVRn bit assignments The TRCCNTRLDVRn registers can be accessed through the internal memory mapped interface and the external debug interface offsets TRCCNTRLDVR0 0x140 TRCCNTRLDVR1 0x144 13 8 21 Counter Control Register 0 The TRCCNTCTLR0 characteristics are Purpose Controls the counter Usage constraints Accepts writes only when the trace unit is disabled Configurations Available in all configura...

Page 527: ...ero The counter only reloads based on RLDTYPE and RLDSEL 1 The counter reloads when it reaches zero and the resource selected by CNTTYPE and CNTSEL is also active The counter also reloads based on RLDTYPE and RLDSEL 15 RLDTYPE Selects the resource type for the reload 0 Single selected resource 1 Boolean combined resource pair 14 12 Reserved RES0 11 8 RLDSEL Selects the resource number based on the...

Page 528: ... decrements based on CNTTYPE and CNTSEL 1 The counter decrements when the counter reloads The counter also decrements when the resource selected by CNTTYPE and CNTSEL is active 16 RLDSELF Defines whether the counter reloads when it reaches zero 0 The counter does not reload when it reaches zero The counter only reloads based on RLDTYPE and RLDSEL 1 The counter reloads when it is zero and the resou...

Page 529: ...re are no usage constraints Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 26 shows the TRCIDR8 bit assignments Figure 13 26 TRCIDR8 bit assignments Table 13 27 shows the TRCIDR8 bit assignments The TRCIDR8 can be accessed through the internal memory mapped interface and the external debug interface offset 0x180 31 16 15 0 R...

Page 530: ...e TRCIDR9 bit assignments The TRCIDR9 can be accessed through the internal memory mapped interface and the external debug interface offset 0x184 13 8 26 ID Register 10 The TRCIDR10 characteristics are Purpose Returns the number of P1 right hand keys that the trace unit can use Usage constraints There are no usage constraints Configurations Available in all configurations Attributes See the registe...

Page 531: ...shows the TRCIDR11 bit assignments The TRCIDR11 can be accessed through the internal memory mapped interface and the external debug interface offset 0x18C 13 8 28 ID Register 12 The TRCIDR12 characteristics are Purpose Returns the number of conditional instruction right hand keys that the trace unit can use Usage constraints There are no usage constraints Configurations Available in all configurat...

Page 532: ...mary in Table 13 3 on page 13 10 Figure 13 31 shows the TRCIDR13 bit assignments Figure 13 31 TRCIDR13 bit assignments Table 13 32 shows the TRCIDR13 bit assignments The TRCIDR13 can be accessed through the internal memory mapped interface and the external debug interface offset 0x194 31 0 NUMCONDKEY Table 13 31 TRCID12 bit assignments Bits Name Function 31 0 NUMCONDKEY The number of conditional i...

Page 533: ... Figure 13 32 TRCIMSPEC0 bit assignments Table 13 33 shows the TRCIMSPEC0 bit assignments The TRCIMSPEC0 can be accessed through the internal memory mapped interface and the external debug interface offset 0x1C0 13 8 31 ID Register 0 The TRCIDR0 characteristics are Purpose Returns the tracing capabilities of the ETM trace unit Usage constraints There are no usage constraints Configurations Availab...

Page 534: ...elements not supported 14 QFILT Indicates Q element filtering support b0 Q element filtering not supported 13 12 CONDTYPE Indicates how conditional results are traced b00 Conditional trace not supported 11 10 NUMEVENT Number of events supported in the trace minus 1 b11 Four events supported 9 RETSTACK Return stack support 1 Return stack implemented 8 Reserved RES0 7 TRCCCI Support for cycle counti...

Page 535: ...13 35 shows the TRCIDR1 bit assignments The TRCIDR1 can be accessed through the internal memory mapped interface and the external debug interface offset 0x1E4 13 8 33 ID Register 2 The TRCIDR2 characteristics are Purpose Returns the maximum size of the following parameters in the trace unit Cycle counter Data value Data address VMID 31 0 RES0 TRCARCHMAJ 24 23 16 15 12 11 8 7 4 3 RES1 DESIGNER REVI...

Page 536: ...d The number of cores available for tracing If an exception level supports instruction tracing The minimum threshold value for instruction trace cycle counting Whether the synchronization period is fixed 31 0 25 24 14 15 10 9 5 4 IASIZE 29 28 20 19 CIDSIZE VMIDSIZE DASIZE DVSIZE CCSIZE RES0 Table 13 36 TRCIDR2 bit assignments Bits Name Function 31 29 Reserved RES0 28 25 CCSIZE Size of the cycle co...

Page 537: ...tes whether TRCSTALLCTLR NOOVERFLOW is implemented 0 TRCSTALLCTLR NOOVERFLOW is not implemented 30 28 NUMPROC Indicates the number of cores available for tracing 0b000 The trace unit can trace one processor ETM trace unit sharing not supported 27 SYSSTALL Indicates whether stall control is implemented 1 The system supports processor stall control 26 STALLCTL Indicates whether TRCSTALLCTLR is imple...

Page 538: ...12 Reserved RES0 11 0 CCITMIN The minimum value that can be programmed in TRCCCCTLR THRESHOLD 0x004 Instruction trace cycle counting minimum threshold is 4 Table 13 37 TRCIDR3 bit assignments continued Bits Name Function 31 0 23 24 16 15 8 7 3 4 27 28 20 19 NUMDVC NUMPC NUMSSCC NUMCIDC NUMACPAIRS 9 11 12 NUMRCPAIRS NUMVMIDC SUPPDAC RES0 Table 13 38 TRCIDR4 bit assignments Bits Name Function 31 28 ...

Page 539: ...rts data address comparisons This value is 0 Data address comparisons are not implemented 7 4 NUMDVC Indicates the number of data value comparators available for tracing 0x0 Data value comparators not implemented 3 0 NUMACPPAIRS Indicates the number of address comparator pairs available for tracing 0x4 Four address comparator pairs are implemented Table 13 38 TRCIDR4 bit assignments continued Bits...

Page 540: ...sabled Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 39 shows the TRCRSCTLRn bit assignments Figure 13 39 TRCRSCTLRn bit assignments 23 LPOVERRIDE Low power state override support 1 Low power state override support implemented 22 ATBTRIG ATB trigger support 1 ATB trigger support implemented 21 16 TRACEIDSIZE Number of bits ...

Page 541: ...R0 bit assignments Table 13 40 TRCSCTLRn bit assignments Bits Name Function 31 22 Reserved RES0 21 PAIRINV Inverts the result of a combined pair of resources This bit is implemented only on the lower register for a pair of resource selectors 20 INV Inverts the selected resources 0 Resource is not inverted 1 Resource is inverted 19 Reserved RES0 18 16 GROUP Selects a group of resources See the ARM ...

Page 542: ...bit assignments Figure 13 41 TRCSSCSR0 bit assignments Table 13 42 shows the TRCSSCSR0 bit assignments 19 16 ARC Selects one or more address range comparators for single shot control One bit is provided for each implemented address range comparator 15 8 Reserved RES0 7 0 SAC Selects one or more single address comparators for single shot control One bit is provided for each implemented single addre...

Page 543: ...nts Figure 13 42 TRCOSLAR bit assignments Table 13 43 shows the TRCOSLAR bit assignments The TRCOSLAR can be accessed through the internal memory mapped interface and the external debug interface offset 0x300 13 8 41 OS Lock Status Register The TRCOSLSR characteristics are Purpose Returns the status of the OS Lock 2 DV Data value comparator support 0 Single shot data value comparisons not supporte...

Page 544: ...e no usage constraints Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 44 on page 13 50 shows the TRCPDCR bit assignments 31 1 0 RES0 OSLM 1 3 2 4 nTT OSLK OSLM 0 Table 13 44 TRCOSLSR bit assignments Bits Name Function 31 4 TRCRSCTLRN 3 OSLM 1 OS Lock model 1 bit This bit is combined with OSLM 0 to form a two bit field that i...

Page 545: ... of the ETM trace unit Usage constraints There are no usage constraints Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 45 shows the TRCPDSR bit assignments Figure 13 45 TRCPDSR bit assignments RES0 RES0 31 4 3 2 0 PU Table 13 45 TRCPDCR bit assignments Bits Name Function 31 4 Reserved RES0 3 PU Powerup request to request tha...

Page 546: ... Function 31 6 Reserved RES0 5 OSLK OS lock status 0 The OS Lock is unlocked 1 The OS Lock is locked 4 2 Reserved RES0 1 STICKYPD Sticky power down state 0 Trace register power has not been removed since the TRCPDSR was last read 1 Trace register power has been removed since the TRCPDSR was last read This bit is set to 1 when power to the ETM trace unit registers is removed to indicate that progra...

Page 547: ...dress comparators Usage constraints Accepts writes only when the trace unit is disabled If software uses two single address comparators as an address range comparator then it must program the corresponding TRCACATR registers with identical values in the following fields TYPE CONTEXTTYPE EXLEVEL_S EXLEVEL_NS Configurations Available in all configurations Attributes See the register summary in Table...

Page 548: ... perform a comparison in Secure state for exception level n 1 The trace unit does not perform a comparison in Secure state for exception level n Note The exception levels are Bit 8 Exception level 0 Bit 9 Exception level 1 Bit 10 Always RES0 Bit 11 Exception level 3 7 4 Reserved RES0 3 2 Context type Controls whether the trace unit performs a Context ID comparison a VMID comparison or both compari...

Page 549: ...9 shows the TRCCIDCVR0 bit assignments The TRCCIDCVR0 can be accessed through the internal memory mapped interface and the external debug interface offset 0x600 13 8 47 VMID Comparator Value Register 0 The TRCVMIDCVR0 characteristics are Purpose Contains a VMID value Usage constraints Accepts writes only when the trace unit is disabled Configurations Available in all configurations Attributes See ...

Page 550: ...ilable in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 50 shows the TRCCIDCCTLR0 bit assignments Figure 13 50 TRCCIDCCTLR0 bit assignments Table 13 51 shows the TRCCIDCCTLR0 bit assignments The TRCCIDCCTLR0 can be accessed through the internal memory mapped interface and the external debug interface offset 0x680 Table 13 50 TRCVMIDCVR0 bit assignment...

Page 551: ...emory mapped interface and the external debug interface offset 0xEE4 13 8 50 Integration Instruction ATB Data Register The TRCITIDATAR characteristics are Purpose Sets the state of the ATDATAMn output pins shown in Table 13 53 on page 13 57 Usage constraints Available when bit 0 of TRCITCTRL is set to 1 The value of the register sets the signals on the output pins when the register is written Conf...

Page 552: ...ATAM 31 2 3 4 5 ATDATAM 23 ATDATAM 15 ATDATAM 7 ATDATAM 0 Table 13 53 TRCITIDATAR bit assignments Bits Name Function 31 5 Reserved RES0 4 ATDATAM 31 Drives the ATDATAM 31 outputa a When a bit is set to 0 the corresponding output pin is LOW When a bit is set to 1 the corresponding output pin is HIGH The TRCITDDATAR bit values correspond to the physical state of the output pins 3 ATDATAM 23 Drives t...

Page 553: ...page 13 10 Figure 13 53 shows the TRCITIATBINR bit assignments Figure 13 53 TRCITIATBINR bit assignments Table 13 54 shows the TRCITIATBINR bit assignments The TRCITIATBINR can be accessed through the internal memory mapped interface and the external debug interface offset 0xEF4 31 0 AFVALIDM Reserved 2 1 ATREADYM Table 13 54 TRCITIATBINR bit assignments Bits Name Function 31 2 Reserved Read undef...

Page 554: ...e internal memory mapped interface and the external debug interface offset 0xEFC 13 8 53 Integration Mode Control Register The TRCITCTRL characteristics are Purpose Enables topology detection or integration testing by putting the ETM trace unit into integration mode Usage constraints ARM recommends that you perform a debug reset after using integration mode Configurations Available in all configur...

Page 555: ...Purpose Sets bits in the claim tag and determines the number of claim tag bits implemented Usage constraints There are no usage constraints Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 56 shows the TRCCLAIMSET bit assignments Figure 13 56 TRCCLAIMSET bit assignments 31 0 RES0 IME 1 Table 13 56 TRCITCTRL bit assignments Bit...

Page 556: ... on page 13 10 Figure 13 57 shows the TRCCLAIMCLR bit assignments Figure 13 57 TRCCLAIMCLR bit assignments Table 13 58 shows the TRCCLAIMCLR bit assignments The TRCCLAIMCLR can be accessed through the internal memory mapped interface and the external debug interface offset 0xFA4 Table 13 57 TRCCLAIMSET bit assignments Bits Name Function 31 4 Reserved RES0 3 0 SET On reads for each bit 0 Claim tag ...

Page 557: ...s This register is accessible as follows Configurations The TRCDEVAFF0 is Architecturally mapped to the AArch64 MPIDR_EL1 31 0 register See Multiprocessor Affinity Register on page 4 15 Architecturally mapped to external TRCDEVAFF0 register There is one copy of this register that is used in both Secure and Non secure states Attributes TRCDEVAFF0 is a 32 bit register Figure 13 58 shows the TRCDEVAF...

Page 558: ...VAFF0 bit assignments Bits Name Function 31 M RES1 30 U Indicates a single core system as distinct from core 0 in a cluster This value is 0 Core is part of a cluster 29 25 Reserved RES0 24 MT Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi threading type approach This value is 0 Performance of cores at the lowest affinity level is largely...

Page 559: ...nts Accessible only from the memory mapped interface Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 59 shows the TRCLAR bit assignments Figure 13 59 TRCLAR bit assignments Table 13 61 shows the TRCLAR bit assignments The TRCLAR can be accessed through the internal memory mapped interface and the external debug interface offs...

Page 560: ... permitted by the system Usage constraints There are no usage constraints Configurations Available in all configurations Attributes See the register summary in Table 13 3 on page 13 10 Figure 13 61 shows the TRCAUTHSTATUS bit assignments Figure 13 61 TRCAUTHSTATUS bit assignments RES0 31 1 0 SLK 2 SLI 3 nTT Table 13 62 TRCLSR bit assignments Bits Name Function 31 3 Reserved RES0 2 nTT Indicates si...

Page 561: ...gister summary in Table 13 3 on page 13 10 Figure 13 62 shows the TRCDEVARCH bit assignments Figure 13 62 TRCDEVARCH bit assignments Table 13 63 TRCAUTHSTATUS bit assignments Bits Name Function 31 8 Reserved RES0 7 6 SNID Secure Non invasive Debug b10 Secure Non invasive Debug implemented but disabled b11 Secure Non invasive Debug implemented and enabled 5 4 SID Secure Invasive Debug b00 Secure In...

Page 562: ...ssignments Figure 13 63 TRCDEVID bit assignments Table 13 65 shows the TRCDEVID bit assignments The TRCDEVID can be accessed through the internal memory mapped interface and the external debug interface offset 0xFC8 13 8 63 Device Type Register The TRCDEVTYPE characteristics are Purpose Indicates the type of the component Table 13 64 TRCDEVARCH bit assignments Bits Name Function 31 21 ARCHITECT De...

Page 563: ...pheral Identification Registers provide standard information required for all CoreSight components They are a set of eight registers listed in register number order in Table 13 67 Only bits 7 0 of each Peripheral ID Register are used with bits 31 8 reserved Together the eight Peripheral ID Registers define a single 64 bit Peripheral ID SUB MAJOR RES0 31 0 4 3 7 8 Table 13 66 TRCDEVTYPE bit assignm...

Page 564: ...ailable in all implementations Attributes TRCPIDR0 is a 32 bit RO management register See the register summary in Table 13 3 on page 13 10 Figure 13 65 shows the TRCPIDR0 bit assignments Figure 13 65 TRCPIDR0 bit assignments Table 13 68 shows the TRCPIDR0 bit assignments Peripheral Identification Register 1 The TRCPIDR1 characteristics are Purpose Provides information to identify a trace component...

Page 565: ...rations Available in all implementations Attributes TRCPIDR2 is a 32 bit RO management register See the register summary in Table 13 3 on page 13 10 Figure 13 67 shows the TRCPIDR2 bit assignments Figure 13 67 TRCPIDR2 bit assignments Table 13 70 shows the TRCPIDR2 bit assignments RES0 31 0 3 4 Part_1 7 8 DES_0 Table 13 69 TRCPIDR1 bit assignments Bits Name Function 31 8 Reserved RES0 7 4 DES_0 0x...

Page 566: ...PIDR3 bit assignments Figure 13 68 TRCPIDR3 bit assignments Table 13 71 shows the TRCPIDR3 bit assignments The TRCPIDR3 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFEC Peripheral Identification Register 4 The TRCPIDR4 characteristics are Purpose Provides information to identify a trace component Usage constraints Only bits 7 0 are valid Ac...

Page 567: ...ters identify ETM trace unit as a CoreSight component The Component ID registers are Component Identification Register 0 Component Identification Register 1 on page 13 73 Component Identification Register 2 on page 13 74 Component Identification Register 3 on page 13 74 Component Identification Register 0 The TRCCIDR0 characteristics are Purpose Provides information to identify a trace component R...

Page 568: ...essed through the internal memory mapped interface and the external debug interface offset 0xFF0 Component Identification Register 1 The TRCCIDR1 characteristics are Purpose Provides information to identify a trace component Usage constraints Only bits 7 0 are valid Accessible only from the memory mapped interface or the external debugger interface Configurations Available in all implementations A...

Page 569: ... summary in Table 13 3 on page 13 10 Figure 13 72 shows the TRCCIDR2 bit assignments Figure 13 72 TRCCIDR2 bit assignments Table 13 76 shows the TRCCIDR2 bit assignments The TRCCIDR2 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFF8 Component Identification Register 3 The TRCCIDR3 characteristics are Purpose Provides information to identify ...

Page 570: ...ble 13 3 on page 13 10 Figure 13 73 shows the TRCCIDR3 bit assignments Figure 13 73 TRCCIDR3 bit assignments Table 13 77 shows the TRCCIDR3 bit assignments The TRCCIDR3 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFFC RES0 31 0 PRMBL_3 7 8 Table 13 77 TRCCIDR3 bit assignments Bits Name Function 31 8 Reserved RES0 7 0 PRMBL_3 0xB1 Preamble b...

Page 571: ...ural events are available to the ETM trace unit through the extended input facility See the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile for more information on PMU events The ETM trace unit uses four extended external input selectors to access the PMU events Each selector can independently select one of the PMU events that are then active for the cycles where the relev...

Page 572: ... This chapter describes the cross trigger interfaces for the Cortex A53 processor It contains the following sections About the cross trigger on page 14 2 Trigger inputs and outputs on page 14 3 Cortex A53 CTM on page 14 4 Cross trigger register summary on page 14 5 Cross trigger register descriptions on page 14 8 ...

Page 573: ...es the debug logic ETM trace unit and PMU to interact with each other and with other CoreSight components This is called cross triggering For example you configure the CTI to generate an interrupt when the ETM trace unit trigger event occurs Figure 14 1 shows the debug system components and the available trigger inputs and trigger outputs Figure 14 1 Debug system components Debug restart Cortex A5...

Page 574: ... This signal is the same as nPMUIRQ with inverted polarity PMU generated interrupt 2 3 4 EXTOUT 0 ETM trace unit external output 5 EXTOUT 1 ETM trace unit external output 6 EXTOUT 2 ETM trace unit external output 7 EXTOUT 3 ETM trace unit external output Table 14 2 Trigger outputs CTI output Name Description 0 EDBGRQ Causes the processor to enter debug state 1 DBGRESTART Causes the processor to ex...

Page 575: ...e cross trigger channel interface is presented in the Cortex A53 processor This module can combine up to four internal channel interfaces corresponding to each core along with one external channel interface In the simplified CTM external channel output is driven by the OR output of all internal channel outputs Each internal channel input is driven by the OR output of internal channel outputs of al...

Page 576: ... Reserved 0x010 CTIINTACK WO CTI Output Trigger Acknowledge Register 0x014 CTIAPPSET RW CTI Application Trigger Set Register 0x018 CTIAPPCLEAR WO CTI Application Trigger Clear Register 0x01C CTIAPPPULSE WO CTI Application Pulse Register 0x020 CTIINEN0 RW CTI Input Trigger to Output Channel Enable Registers 0x024 CTIINEN1 RW 0x028 CTIINEN2 RW 0x02C CTIINEN3 RW 0x030 CTIINEN4 RW 0x034 CTIINEN5 RW 0x...

Page 577: ... RO CTI Device ID Register 2 0xFC4 CTIDEVID1 RO CTI Device ID Register 1 0xFC8 CTIDEVID RO CTI Device Identification Register on page 14 8 0xFCC CTIDEVTYPE RO CTI Device Type Register 0xFD0 CTIPIDR4 RO Peripheral Identification Register 4 on page 14 13 0xFD4 CTIPIDR5 RO Peripheral Identification Register 5 7 on page 14 14 0xFD8 CTIPIDR6 RO 0xFDC CTIPIDR7 RO 0xFE0 CTIPIDR0 RO Peripheral Identificat...

Page 578: ...s permission of the register and scanning stops Table 14 4 External register conditions Name Condition Description Off EDPRSR PU is 0 Processor power domain is completely off or in a low power state where the processor power domain registers cannot be accessed DLK EDPRSR DLK is 1 OS Double Lock is locked OSLK OSLSR_EL1 OSLK is 1 OS Lock is locked EDAD AllowExternalDebugAccess FALSE External debug ...

Page 579: ...t assignments Figure 14 2 CTIDEVID bit assignments Table 14 6 shows the CTIDEVID bit assignments Off DLK OSLK EDAD SLK Default RO RO 31 0 NUMCHAN 15 14 13 INOUT 4 7 6 5 8 16 21 22 23 24 25 26 RES0 RES0 NUMTRIG EXTMAXNUM RES0 RES0 Table 14 6 CTIDEVID bit assignments Bits Name Function 31 26 Reserved RES0 25 24 INOUT Input and output options Indicates the presence of an input gate The possible value...

Page 580: ... by condition code is Table 14 4 on page 14 7 describes the condition codes Configurations CTIITCTRL is in the Debug power domain Attributes See the register summary in Table 14 3 on page 14 5 Figure 14 3 shows the CTIITCTRL bit assignments Figure 14 3 CTIITCTRL bit assignments Table 14 7 shows the CTIITCTRL bit assignments CTIITCTRL can be accessed through the internal memory mapped interface and...

Page 581: ...on page 14 12 Peripheral Identification Register 4 on page 14 13 Peripheral Identification Register 5 7 on page 14 14 Peripheral Identification Register 0 The CTIPIDR0 characteristics are Purpose Provides information to identify a CTI component Usage constraints The accessibility of CTIPIDR0 by condition code is Table 14 4 on page 14 7 describes the condition codes Configurations CTIPIDR0 is in th...

Page 582: ...rations CTIPIDR1 is in the Debug power domain CTIPIDR1 is optional to implement in the external register interface Attributes See the register summary in Table 14 3 on page 14 5 Figure 14 5 shows the CTIPIDR1 bit assignments Figure 14 5 CTIPIDR1 bit assignments Table 14 10 shows the CTIPIDR1 bit assignments RES0 31 0 7 8 Part_0 Table 14 9 CTIPIDR0 bit assignments Bits Name Function 31 8 Reserved R...

Page 583: ... register interface Attributes See the register summary in Table 14 3 on page 14 5 Figure 14 6 shows the CTIPIDR2 bit assignments Figure 14 6 CTIPIDR2 bit assignments Table 14 11 shows the CTIPIDR2 bit assignments CTIPIDR2 can be accessed through the internal memory mapped interface and the external debug interface offset 0xFE8 Peripheral Identification Register 3 The CTIPIDR3 characteristics are ...

Page 584: ...ped interface and the external debug interface offset 0xFEC Peripheral Identification Register 4 The CTIPIDR4 characteristics are Purpose Provides information to identify a CTI component Usage constraints The accessibility of CTIPIDR4 by condition code is Table 14 4 on page 14 7 describes the condition codes Configurations CTIPIDR4 is in the Debug power domain CTIPIDR4 is optional to implement in ...

Page 585: ...e Component ID registers are Component Identification Register 0 Component Identification Register 1 on page 14 15 Component Identification Register 2 on page 14 16 Component Identification Register 3 on page 14 17 Component Identification Register 0 The CTICIDR0 characteristics are Purpose Provides information to identify a CTI component RES0 31 0 3 4 DES_2 7 8 Size Table 14 13 CTIPIDR4 bit assig...

Page 586: ... internal memory mapped interface and the external debug interface offset 0xFF0 Component Identification Register 1 The CTICIDR1 characteristics are Purpose Provides information to identify a CTI component Usage constraints The accessibility of CTICIDR1 by condition code is Table 14 4 on page 14 7 describes the condition codes Configurations CTICIDR1 is in the Debug power domain CTICIDR1 is option...

Page 587: ...le 14 4 on page 14 7 describes the condition codes Configurations CTICIDR2 is in the Debug power domain CTICIDR2 is optional to implement in the external register interface Attributes See the register summary in Table 14 3 on page 14 5 Figure 14 11 shows the CTICIDR2 bit assignments Figure 14 11 CTICIDR2 bit assignments Table 14 17 shows the CTICIDR2 bit assignments RES0 31 0 PRMBL_1 7 8 3 4 CLASS...

Page 588: ...14 7 describes the condition codes Configurations CTICIDR3 is in the Debug power domain CTICIDR3 is optional to implement in the external register interface Attributes See the register summary in Table 14 3 on page 14 5 Figure 14 12 shows the CTICIDR3 bit assignments Figure 14 12 CTICIDR3 bit assignments Table 14 18 shows the CTICIDR3 bit assignments CTICIDR3 can be accessed through the internal m...

Page 589: ... 5 Generic Interrupt Controller signals on page A 6 Generic Timer signals on page A 8 Power management signals on page A 9 L2 error signals on page A 11 ACE and CHI interface signals on page A 12 CHI interface signals on page A 13 ACE interface signals on page A 17 ACP interface signals on page A 22 External debug interface on page A 25 ATB interface signals on page A 28 Miscellaneous ETM trace un...

Page 590: ... four cores For example nIRQ 0 represents a core 0 interrupt request nIRQ 2 represents a core 2 interrupt request Some signals are specified in the form signal x where x 0 1 2 or 3 to reference core 0 core 1 core 2 core 3 If a core is not present the corresponding pin is removed For example PMUEVENT0 29 0 represents the core 0 PMU event bus PMUEVENT3 29 0 represents the core 3 PMU event bus The nu...

Page 591: ...ns ARM DDI 0500D Copyright 2013 2014 ARM All rights reserved A 3 ID021414 Non Confidential A 2 Clock signals Table A 1 shows the clock signal Table A 1 Clock signal Signal Direction Description CLKIN Input Global clock ...

Page 592: ...uding Debug and ETM trace unit 0 Apply reset to processor logicb 1 Do not apply reset to processor logicb nL2RESET Input L2 memory system reset 0 Apply reset to shared L2 memory system controller 1 Do not apply reset to shared L2 memory system controller L2RSTDISABLE Input Disable automatic L2 cache invalidate at reset 0 Hardware resets L2 cache 1 Hardware does not reset L2 cache WARMRSTREQ CN 0 O...

Page 593: ...essor CLUSTERIDAFF1 7 0 Input Value read in the Cluster ID Affinity Level 1 field MPIDR bits 15 8 of the CP15 MPDIR register These pins are sampled only during reset of the processor CLUSTERIDAFF2 7 0 Input Value read in the Cluster ID Affinity Level 2 field MPIDR bits 23 16 of the CP15 MPDIR register These pins are sampled only during reset of the processor CP15SDISABLE CN 0 Input Disable write a...

Page 594: ...nput must be asserted until the processor acknowledges the interrupt If the GIC is enabled by tying the GICCDISABLE input pin LOW the nVFIQ input pin must be tied off to HIGH If the GIC is disabled by tying the GICCDISABLE input pin HIGH the nVFIQ input pin can be driven by an external GIC in the SoC nVIRQ CN 0 Input Virtual IRQ request Active LOW level sensitive asynchronous interrupt request 0 A...

Page 595: ...Protocol signal Distributor to GIC CPU Interface messages TLAST indicates the boundary of a packet ICDTDEST 1 0 Input AXI4 Stream Protocol signal Distributor to GIC CPU Interface messages TDEST provides routing information for the data stream ICCTVALID Output AXI4 Stream Protocol signal GIC CPU Interface to Distributor messages TVALID indicates that the master is driving a valid transfer ICCTREADY...

Page 596: ...Signal Direction Description nCNTHPIRQ CN 0 Output Hypervisor physical timer event nCNTPNSIRQ CN 0 Output Non secure physical timer event nCNTPSIRQ CN 0 Output Secure physical timer event nCNTVIRQ CN 0 Output Virtual physical timer event CNTCLKEN Input Counter clock enable This clock enable must be inserted one cycle before the CNTVALUEB bus CNTVALUEB 63 0 Input Global system counter value in bina...

Page 597: ...NDBYWFI CN 0 Output Indicates whether a core is in WFI low power state 0 Core not in WFI low power state 1 Core in WFI low power state This is the reset condition STANDBYWFE CN 0 Output Indicates whether a core is in WFE low power state 0 Core not in WFE low power state 1 Core in WFE low power state STANDBYWFIL2 Output Indicates whether the L2 memory system is in WFI low power state This signal is...

Page 598: ...referenced Advanced SIMD and Floating point block is active NEONQREQn CN 0 Input Indicates that the power controller is ready to enter or exit retention for the referenced Advanced SIMD and Floating point block NEONQDENY CN 0 Output Indicates that the referenced Advanced SIMD and Floating point block denies the power controller retention request NEONQACCEPTn CN 0 Output Indicates that the referenc...

Page 599: ...nals Table A 8 shows the L2 error signals Table A 8 L2 error signals Signal Direction Description nEXTERRIRQ Output Error indicator for AXI or CHI transactions with a write response error condition See External aborts handling on page 7 18 for more information nINTERRIRQ Output Error indicator for L2 RAM double bit ECC error ...

Page 600: ...m caches This pin is sampled only during reset of the Cortex A53 processor BROADCASTINNERa Input Enable broadcasting of Inner Shareable transactions 0 Inner Shareable transactions are not broadcast externally 1 Inner Shareable transactions are broadcast externally If BROADCASTINNER is tied HIGH you must also tie BROADCASTOUTER HIGH This pin is sampled only during reset of the Cortex A53 processor ...

Page 601: ...10 2 Transmit request virtual channel signals Table A 11 shows the transmit request virtual channel signals Table A 10 Clock and configuration signals Signal Direction Description SCLKEN Input CHI interface bus clock enable SINACT Input CHI snoop active NODEID 6 0 Input Cortex A53 CHI Node Identifier RXSACTIVE Input Receive pending activity indicator TXSACTIVE Output Transmit pending activity indi...

Page 602: ... Transmit response flit pending TXRSPFLITV Output Transmit response flit valid TXRSPFLIT 44 0 Output Transmit response flit TXRSPLCRDV Input Transmit response link layer credit valid Table A 13 Transmit data virtual channel signals Signal Direction Description TXDATFLITPEND Output Transmit data flit pending TXDATFLITV Output Transmit data flit valid TXDATFLIT 193 0 Output Transmit data flit TXDATL...

Page 603: ... flit valid RXDATFLIT 193 0 Input Receive data flit RXDATLCRDV Output Receive data link layer credit valid Table A 17 System address map signals Signal Direction Description SAMADDRMAP0 1 0 Input Region mapping 0 512MB SAMADDRMAP1 1 0 Input Region mapping 512MB 1GB SAMADDRMAP2 1 0 Input Region mapping 1GB 1 5GB SAMADDRMAP3 1 0 Input Region mapping 1 5GB 2GB SAMADDRMAP4 1 0 Input Region mapping 2GB...

Page 604: ...SAMHNF0NODEID 6 0 Input HN F 0 node ID SAMHNF1NODEID 6 0 Input HN F 1 node ID SAMHNF2NODEID 6 0 Input HN F 2 node ID SAMHNF3NODEID 6 0 Input HN F 3 node ID SAMHNF4NODEID 6 0 Input HN F 4 node ID SAMHNF5NODEID 6 0 Input HN F 5 node ID SAMHNF6NODEID 6 0 Input HN F 6 node ID SAMHNF7NODEID 6 0 Input HN F 7 node ID SAMHNFMODE 2 0 Input HN F interleaving module a SAMMNBASE must reside in a SAMADDRMAPx 1...

Page 605: ...ocessor is configured to have the ACE interface All ACE channels must be balanced with respect to CLKIN and timed relative to ACLKENM A 11 1 Clock and configuration signals Table A 18 shows the clock and configuration signals for the ACE interface Table A 18 Clock and configuration signals Signal Direction Description ACLKENM Input ACE Master bus clock enable See Clocks on page 2 9 for more inform...

Page 606: ...MAINM 1 0 Output Write shareability domain type AWIDM 4 0 Output Write address ID AWLENM 7 0 Output Write burst length AWLOCKM Output Write lock type AWPROTM 2 0 Output Write protection type AWREADYM Input Write address ready AWSIZEM 2 0 Output Write burst size AWSNOOPM 2 0 Output Write snoop request type AWUNIQUEM Output For WriteBack WriteClean and WriteEvict transactions Indicates that the writ...

Page 607: ...e BVALIDM Input Write response valid Table A 22 Read address channel signals Signal Direction Description ARADDRM 43 0 Output Read address The top 4 bits communicate only the ACE virtual address for DVM messages The top 4 bits are Read as Zero if a DVM message is not being broadcast ARBARM 1 0 Output Read barrier type ARBURSTM 1 0 Output Read burst type ARCACHEM 3 0 Output Read cache type ARDOMAIN...

Page 608: ...AM 127 0 Input Read data RIDM 5 0 Input Read data ID RLASTM Input Read data last transfer indication RREADYM Output Read data ready RRESPM 3 0 Input Read data response RVALIDM Input Read data valid Table A 24 Coherency address channel signals Signal Direction Description ACADDRM 43 0 Input Snoop address The top 4 bits communicate only the ACE virtual address for DVM messages ACPROTM 2 0 Input Snoo...

Page 609: ...acknowledge signals Table A 27 shows the read write acknowledge signals for the ACE master interface Table A 26 Coherency data channel handshake signals Signal Direction Description CDDATAM 127 0 Output Snoop data CDLASTM Output Snoop data last transform CDREADYM Input Slave ready to accept snoop data CDVALIDM Output Snoop data valid Table A 27 Read and write acknowledge signals Signal Direction D...

Page 610: ...onfiguration signals for the ACP interface A 12 2 Write address channel signals Table A 29 shows the write address channel signals for the ACP interface Table A 28 Clock and Configuration signals Signal Direction Description ACLKENS Input AXI slave bus clock enable AINACTS Input ACP master is inactive and is not participating in coherency There must be no outstanding transactions when the master a...

Page 611: ...ite protection type Table A 29 Write address channel signals continued Signal Direction Description Table A 30 Write data channel signals Signal Direction Description WREADYS Output Write data ready WVALIDS Input Write data valid WDATAS 127 0 Input Write data WSTRBS 15 0 Input Write byte lane strobes WLASTS Input Write data last transfer indication Table A 31 Write response channel signals Signal ...

Page 612: ...ad cache type ARUSERS 1 0 Input Read attributes 0 Inner Shareable 1 Outer Shareable ARPROTS 2 0 Input Read protection type Table A 32 Read address channel signals continued Signal Direction Description Table A 33 Read data channel signals Signal Direction Description RREADYS Input Read data ready RVALIDS Output Read data valid RIDS 4 0 Output Read data ID RDATAS 127 0 Output Read data RRESPS 1 0 O...

Page 613: ...nals Signal Direction Description nPRESETDBG Input APB reset active LOW 0 Apply reset to APB interface 1 Do not apply reset to APB interface PADDRDBG 21 2 Input APB address bus PADDRDBG31 Input APB address bus bit 31 0 Not an external debugger access 1 External debugger access PCLKENDBG Input APB clock enable PENABLEDBG Input Indicates the second and subsequent cycles of an APB transfer PRDATADBG ...

Page 614: ...COMMRX CN 0 Output Communications channel receive Receive portion of Data Transfer Register full flag 0 Empty 1 Full COMMTX CN 0 Output Communication transmit channel Transmit portion of Data Transfer Register empty flag 0 Full 1 Empty EDBGRQ CN 0 Input External debug request 0 No external debug request 1 External debug request The processor treats the EDBGRQ input as level sensitive The EDBGRQ in...

Page 615: ...request to the power controller 1 Power up request to the power controller DBGL1RSTDISABLE Input Disable L1 data cache automatic invalidate on reset functionality 0 Enable automatic invalidation of L1 data cache on reset 1 Disable automatic invalidation of L1 data cache on reset This pin is sampled only during reset of the processor Table A 35 Miscellaneous Debug signals continued Signal Direction...

Page 616: ...e all ATB interface signals with respect to CLKIN and time them relative to ATCLKEN Table A 36 ATB interface signals Signal Direction Description ATCLKEN Input ATB clock enable ATREADYMx Input ATB device ready AFVALIDMx Input FIFO flush request ATDATAMx 31 0 Output Data ATVALIDMx Output Data valid ATBYTESMx 1 0 Output Data size AFREADYMx Output FIFO flush finished ATIDMx 6 0 Output Trace source ID...

Page 617: ... Confidential A 15 Miscellaneous ETM trace unit signals Table A 37 shows the miscellaneous ETM trace unit signals Table A 37 Miscellaneous ETM trace unit signals Signal Direction Description SYNCREQMx Input Synchronization request from trace sink TSVALUEB 63 0 Input Timestamp in binary encoding ...

Page 618: ...CTI interface signals Signal Direction Description CTICHIN 3 0 Input Channel In CTICHOUTACK 3 0 Input Channel Out acknowledge CTICHOUT 3 0 Output Channel Out CTICHINACK 3 0 Output Channel In acknowledge CISBYPASS Input Channel interface sync bypass CIHSBYPASS 3 0 Input Channel interface H S bypass CTIIRQ CN 0 Output CTI interrupt active HIGH CTIIRQACK CN 0 Input CTI interrupt acknowledge ...

Page 619: ...ll rights reserved A 31 ID021414 Non Confidential A 17 PMU interface signals Table A 39 shows the PMU interface signals Table A 39 PMU interface signals Signal Direction Description PMUEVENTx 29 0 Output PMU event bus nPMUIRQ CN 0 Output PMU interrupt request ...

Page 620: ...ace ports are internally tied off in the design and you can insert MBIST into the design before synthesis The process of adding MBIST into the design can be done automatically by an EDA MBIST tool Table A 40 DFT interface signals Signal Direction Description DFTRAMHOLD Input Disable the RAM chip select during scan testing DFTRSTDISABLE Input Disable internal synchronized reset during scan shift DF...

Page 621: ...haviors for each UNPREDICTABLE case A single preferred behavior for each UNPREDICTABLE case from that range of legal behaviors Where possible and practical all ARM implementations adhere to these single preferred behaviors In some limited instances an ARM implementation might not adhere to these single preferred behaviors and instead behaves as described by one of the alternate legal behaviors The...

Page 622: ...Behaviors ARM DDI 0500D Copyright 2013 2014 ARM All rights reserved B 2 ID021414 Non Confidential Load Store accesses crossing page boundaries on page B 5 ARMv8 Debug unpredictable behaviors on page B 6 Other unpredictable behaviors on page B 11 ...

Page 623: ...A architecture profile read 0 unless otherwise stated in section 4 28 or as described in the following paragraph If the use of R15 as a base register for a load or store is UNPREDICTABLE the value used by the load or store using R15 as a base register is the Program Counter PC with its usual offset and in the case of T32 instructions with the forced word alignment In this case if the instruction s...

Page 624: ...ions within an IT Block described as being UNPREDICTABLE in the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile pseudo code are executed unconditionally Implementation The Cortex A53 processor does not implement an unconditional execution policy for the following instructions Instead all execute conditionally NEON instructions new to ARMv8 All instructions in the ARMv8 Cry...

Page 625: ...f the ARM Architecture Reference Manual ARMv8 for ARMv8 A architecture profile having memory accesses from one load or store instruction to Device or Strongly ordered memory cross a 4 KB boundary is UNPREDICTABLE In this situation the implementation Performs all memory accesses from this instruction as if the presence of the boundary had no effect on the memory accesses Implementation for both pag...

Page 626: ...struction with condition code not AL The Cortex A53 processor implements the preferred option Option 3 executed unconditionally B 4 2 Address match breakpoint match only on second halfword of an instruction The Cortex A53 processor generates a breakpoint on the instruction unless it is a breakpoint on the second half of the first 32 bit instruction In this case the breakpoint is taken on the follo...

Page 627: ... T32 instruction at vector 2 The Cortex A53 processor implements Option 1 Does match B 4 12 Address matching Vector catch and Breakpoint on same instruction The Cortex A53 processor implements Option 2 Report Breakpoint B 4 13 Address match breakpoint with DBGBCRn_EL1 BAS 0000 The Cortex A53 processor implements Option 1 As if disabled B 4 14 DBGWCRn_EL1 BAS specifies a non contiguous set of bytes...

Page 628: ...or this generates a Vector catch debug event Note The debug event is subject to the same CONSTRAINED UNPREDICTABLE behavior and so the Vector catch debug event is repeatedly generated an UNKNOWN number of times B 4 19 H N or H 0 at Non secure EL1 and EL0 including value read from PMCR_EL0 N The Cortex A53 processor implements A simple implementation where all of HPMN 4 0 are implemented and In Non...

Page 629: ...eated gathered split or resized in accordance with the rules for Normal memory meaning the effect is UNPREDICTABLE B 4 28 Not word sized accesses or AArch64 only doubleword sized accesses The Cortex A53 processor behaves as indicated in the sole Preference Reads occur and return UNKNOWN data Writes set the accessed register s to UNKNOWN B 4 29 External debug write to register that is being reset T...

Page 630: ...bug access is disabled 3 For reserved Performance Monitor registers in the address ranges 0x000 to 0x0FC and 0x400 to 0x47C the response is CONSTRAINED UNPREDICTABLE Error or RES0 when the conditions in 1 and 2 do not apply and the following errors instead of preferred res0 for the these registers EPMAD AllowExternalPMUAccess is FALSE external Performance Monitors access is disabled B 4 31 Clearin...

Page 631: ...The CCSIDR read is UNDEFINED The CCSIDR read returns an UNKNOWN value preferred B 5 2 HDCR HPMN is set to 0 or to a value larger than PMCR N If HDCR HPMN is set to 0 or to a value larger than PMCR N then the behavior in Non secure EL0 and EL1 is CONSTRAINED UNPREDICTABLE and one of the following must happen The number of counters accessible is an UNKNOWN non zero value less than PMCR N There is no...

Page 632: ...wn sequence updated Cluster shutdown mode without system driven L2 flush on page 2 22 All revisions Revision information updated Chapter 4 System Control r0p1 GIC programmers model on page 9 3 ETM register descriptions on page 13 13 Peripheral Identification Register 2 on page 11 29 Peripheral Identification Register 2 on page 12 29 Peripheral Identification Register 2 on page 14 12 Peripheral Ide...

Page 633: ...ions Removed reference to T32EE ThumbEE ARM architecture on page 1 3 All revisions Updated notes in descriptions of PCLKENDBG ATCLKEN and CNTCLKEN signals Clocks on page 2 9 All revisions Updated list of supported core power states Supported core power states on page 2 18 All revisions Revision information updated Chapter 4 System Control r0p2 GIC programmers model on page 9 3 ETM register descrip...

Page 634: ... the ROM table Peripheral Identification Registers on page 11 45 All revisions Updated PMU register summary table Table 12 9 on page 12 14 All revisions Peripheral identification and Component identification register names changed in Memory mapped PMU register summary Table 12 15 on page 12 23 All revisions Updated ETM exception level information Table 13 1 on page 13 3 All revisions Updated ETM p...

Page 635: ...ibute Indirection Register EL3 on page 4 118 Memory Attribute Indirection Registers 0 and 1 on page 4 259 All revisions Instruction mnemonic updated 64 bit registers on page 4 147 All revisions Added note to CPUECTLR SMPEN bit description Table 4 245 on page 4 273 All revisions SELx signal reduced from 6 bits to 5 bits Figure 13 21 on page 13 30 Table 13 22 on page 13 30 All revisions Updated numb...

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