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Link Layer Tests
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Examiner will be enumerated by the host PUT as a device.
2.
Examiner software prompts the test operator to put the host controller machine to sleep.
3.
Examiner waits to receive an LGO_U3 from the PUT.
4.
Examiner sends an LAU when it receives an LGO_U3 from the PUT.
5.
Examiner waits to receive an LPMA from the PUT.
The test fails if Examiner does not receive an LGO_U3, LPMA, or fails to
transition to U3.
6.
Examiner prompts the test operator to verify that the host controller machine is in a sleep
state.
7.
Examiner prompts the test operator to wake the host controller machine.
8.
Examiner waits to receive a U3 Exit LFPS from the PUT.
The test fails if no U3 Exit LFPS was sent.
9.
Examiner sends a U3 Exit LFPS and Examiner and PUT transition through Recovery to U0
(and stays there for 50ms).
The test passes after the Port Configuration transaction if all exchanges are
correct.
Specification Reference
Sections 7.2.4.2.4#1,4,5 ● 7.2.4.2.7#1 ● 7.5.9.1#4 ● 7.5.9.2#5
7.37
Packet Pending Test (Upstream Port Only)
Test Summary
This test verifies the PUT releases its Packet Pending (PP) flag at the end of a control transfer.
Test Steps and Expected Results
1.
Perform the Link Initialization Sequence to bring Examiner and PUT link to U0.
